-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
1.0E+3
1.0E+4
1.0E+5
1.0E+6
PSA3230A
Telecommunications
Satellite
Telemetry
5
50
3205
-70
0.7
-15
1
1
-40 to 85
Frequency Range
RMS Phase Error (100 Hz - 100 KHz)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
Package Style
PLL-24
MHz
°
dBc
dBc
mSec
mSec
°C
Vdc
mA
Supply Voltage (Vcc, nom.)
Supply Current (Icc, typ.)
All specifications are typical unless otherwise noted and subject to change without notice.
PHASE NOISE (1 Hz BW, typical)
© Z-Communications, Inc.
All rights reserved
Page 1
PHASE LOCKED LOOP
FEATURES
APPLICATIONS
PERFORMANCE SPECIFICATIONS
VALUE
UNITS
POWER SUPPLY REQUIREMENTS
APPLICATION NOTES
3205
MHz
·
Step Size:
125 KHz
- Style Package
PLL-24
·
·
·
·
B2
Rev
·
AN-107 : How to Solder Z-COMM VCOs / PLLs
·
AN-200 : Mounting and Grounding of Z-COMM PLLs
·
AN-201 : PLL Fundamentals AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<
f
osc
<100 MHz Prescaler: 32
Frequency Synthesizer: Analog Devices - ADF4106
9939 Via Pasar · San Diego, CA 92126
TEL (858) 621-2700 FAX (858) 621-2722
Power Output
-1±3
dBm
Load Impedance
50
Step Size
125
KHz
5000
3235
-
· Frequency Range:
-
3235
Charge Pump Output Current
µ
3 1 6 0
3 1 8 0
3 2 0 0
3 2 2 0
3 2 4 0
3 2 6 0
3 2 8 0
3 3 0 0
0
0 . 5
1
1 . 5
2
2 . 5
3
3 . 5
4
-5
-4
-3
-2
-1
0
1
2
3
3 1 7 7
3 1 8 5
3 1 9 3
3 2 0 3
3 2 1 4
3 2 2 6
3 2 3 9
3 2 5 3
3 2 6 7
LOW COST - HIGH PERFORMANCE
PHASE LOCKED LOOP
© Z-Communications, Inc.
Page 2
Printed in the U.S.A.
PSA3230A
VCO POWER CURVE, typ.
PAGE 2
PHYSICAL DIMENSIONS
0.
14
0
.0
3
2
17
19
15
13
1
2
3
4
8
10
12
24
22
20
5
6
7
9
11
14
16
18
21
23
TOP
P1 RF OUTPUT
P2-4 GROUND
P5 REFERENCE OSCILLATOR INPUT
P6 GROUND
P7 CLOCK
P8 DATA
P9 GROUND
P10 LOAD ENABLE
P11 GROUND
P12 LOCK DETECT
P13 VCC
P14 GROUND
P15 GROUND
P16 GROUND
P17 NO CONNECTION
P18-24 GROUND
TABS RANGE:
SEE NOTE 5
DETAIL A
.015
.030
.055
DETAIL B (TYP)
(8 PLACES)
SIDE VIEW
1.
The inside radius of all 24 half holes at the perimeter of
the board are plated to provide a surface for the
attachment of the PLL Module to the PCB. 16 pads are
for grounding, 8 pads are for signal interface.
2.
The surface of the shield is tin-plated and may be
soldered to. The shield's base metal is cold-rolled steel.
3.
The ground plane on the bottom side is ground and
attaches to a ground track on the top side of the board
as well as to the shield.
4.
Unless otherwise noted all dimensions are in inches.
5.
Unless otherwise noted all tolerances are as follows:
.xxx =
±
.010.
SEE DETAIL A
SEE DETAIL B
PIN 1
BOTTOM
.000
.153
.238
.323
.408
.493
.578
.663
-.025
.841
.0
0
0
.1
1
5
.2
0
0
.2
8
5
.3
7
0
.4
5
5
.5
8
0
-.
02
6
.6
0
5
.816
°c
25
VCO TUNING CURVE, typ.
FREQUENCY (MHz)
TUNING VOLTAGE (Vdc)
°c
25
°c
-40
°c
85
FREQUENCY (MHz)
OUTPUT POWER (dBm)
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