Document Outline

Features
Applications
- Figure 1 - Block Diagram
- Pin Description
1.0 Functional Description
- 1.1 DPLL Features
  - Table 1 - DPLL1 and DPLL2 Features
- 1.2 DPLL Mode Control
  - Figure 2 - Automatic Mode State Machine
- Free-run
- Lock Acquisition
- Normal (locked)
- Holdover
- 1.3 Ref and Sync Inputs
  - Figure 3 - Reference and Sync Inputs
  - Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
  - Figure 4 - Output Frame Pulse Alignment
  - Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
- 1.4 Ref and Sync Monitoring
- Single Cycle Monitor (SCM)
- Coarse Frequency Monitor (CFM)
- Precise Frequency Monitor (PFM)
  - Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures
- 1.5 Output Clocks and Frame Pulses
  - Figure 6 - Output Clock Configuration
  - Table 4 - Output Clock and Frame Pulse Frequencies
- 1.6 Configurable Input-to-Output and Output-to-Output Delays
  - Figure 7 - Phase Delay Adjustments
- 1.7 Master/Slave Configuration
  - Figure 8 - Typical Master/Slave Configuration
- 1.8 External Feedback Inputs
  - Figure 9 - External Feedback Configuration
2.0 Software Configuration
- Table 5 - Register Map
3.0 References

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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To register, please send an email to
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Features

· Supports the requirements of Telcordia GR-253 and

GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and

the requirements of ITU-T G.781 SETS, G.813

SEC, G.823, G.824 and G.825 clocks

· Internal APLL provides standard output clock

frequencies up to 622.08 MHz with jitter < 1 ps

RMS suitable for OC-48/STM-16 interfaces

· Programmable output synthesizers generate clock

frequencies from any multiple of 8 kHz up to

77.76 MHz in addition to 2 kHz

· Provides two DPLLs which are independently

configurable through a serial software interface

· DPLL1 provides all the features necessary for

generating SONET/SDH compliant clocks including

automatic hitless reference switching, automatic

mode selection (locked, free-run, holdover),

selectable loop bandwidth and pull-in range

· DPLL2 provides a comprehensive set of features

necessary for generating derived output clocks and

other general purpose clocks

· Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

· Supports master/slave configuration for

AdvancedTCA

· Configurable input to output delay and output to

output phase alignment

· Optional external feedback path provides dynamic

input to output delay compensation

· Provides 3 sync inputs for output frame pulse

alignment

· Generates several styles of output frame pulses

with selectable pulse width, polarity and frequency

· Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

· Supports IEEE 1149.1 JTAG Boundary Scan

December 2005

Figure 1 - Block Diagram

dpll1_mod_sel1:0

tck

tdo

tdi tms

trst_b

dpll1_holdover

dpll1_lock

DPLL2

sck

DPLL1

slave_en

dpll2_ref

rst_b

dpll1_hs_en

cs_b

diff0_en

diff1_en

Reference

Monitors

ref

sync

ref

ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7

sync0
sync1
sync2

int_b

sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1

p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1

fb_clk

ref7:0

sync2:0

ref_&_sync_status

Controller &

State Machine

SPI Interface

SONET/SDH

APLL

Synthesizer

Feedback

Synthesizer

diff0

diff1

IEEE 1449.1

JTAG

Master

Clock

fb_clk

ext_fb_clk

ext_fb_fp

osco
osci

fb_fp

sdh_filter filter_ref0

filter_ref1

ZL30116

SONET/SDH

Low Jitter System Synchronizer

Data Sheet

Ordering Information

ZL30116GGG

100 Pin CABGA

Trays

ZL30116GGG2

100 Pin CABGA* Trays

*Pb Free Tin/Silver/Copper

-40

C to +85

ZL30116

Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ZL30116

Data Sheet

List of Figures

Zarlink Semiconductor Inc.

Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - Typical Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 - External Feedback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ZL30116

Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5 - Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Part Number ZL30116GGG

Document Outline