SPICE Device Model Si9430DY
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70512
www.vishay.com
01-Jun-04
1
P-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
· P-Channel Vertical DMOS
· Macro Model (Subcircuit Model)
· Level 3 MOS
· Apply for both Linear and Switching Application
· Accurate over the -55 to 125°C Temperature Range
· Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125°C
temperature ranges under the pulsed 0 to 5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model Si9430DY
Vishay Siliconix
www.vishay.com
Document Number: 70512
2
01-Jun-04
SPECIFICATIONS (T
J
= 25
°C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Conditions
Typical
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
=
-250 µA
2.2 V
V
DS
=
-5 V, V
GS
=
-10 V
117
On-State Drain Current
a
I
D(on)
V
DS
=
-5 V, V
GS
=
-4.5 V
14
A
V
GS
=
-10 V, I
D
=
-5.3 A
0.033
V
GS
=
-6 V, I
D
=
-3.6 A
0.042
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
-4.5 V, I
D
=
- 2.0 A
0.055
Forward Transconductance
a
g
fs
V
DS
=
-15 V, I
D
=
-5.3 A
9.3 S
Diode Forward Voltage
a
V
SD
I
S
=
-2.4 A, V
GS
= 0 V
-0.76
V
Dynamic
b
Total Gate Charge
b
Q
g
26.4
Gate-Source Charge
b
Q
gs
4.5
Gate-Drain Charge
b
Q
gd
V
DS
=
-10 V, V
GS
=
-10 V, I
D
=
-5.3 A
5.6
nC
Turn-On Delay Time
b
t
d(on)
15
Rise Time
b
t
r
21
Turn-Off Delay Time
b
t
d(off)
35
Fall Time
b
t
f
V
DD
=
-10 V, R
L
= 10
I
D
-1 A, V
GEN
=
-10 V, R
G
= 6
45
Source-Drain Reverse Recovery Time
t
rr
I
F
=
-2.4A, di/dt = 100 A/µs
66
ns
Notes
a. Pulse test; pulse width
300 µs, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
SPICE Device Model Si9430DY
Vishay Siliconix
Document Number: 70512
www.vishay.com
01-Jun-04
3
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
°C UNLESS OTHERWISE NOTED)
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