Vishay Siliconix
SPICE Device Model Si3495DV
P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
· P-Channel Vertical DMOS
· Macro Model (Subcircuit Model)
· Level 3 MOS
· Apply for both Linear and Switching Application
· Accurate over the -55 to 125°C Temperature Range
· Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
1
www.vishay.com
Document Number: 73150
S-50836
Rev. B, 16-May-05
Vishay Siliconix
SPICE Device Model Si3495DV
SPECIFICATIONS (T
J
= 25
°C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
=
-250 µA
0.66 V
On-State Drain Current
ba
I
D(on)
V
DS
=
-5 V, V
GS
=
-4.5 V
144 A
V
GS
=
-4.5 V, I
D
=
-7 A
0.021 0.020
V
GS
=
-2.5 V, I
D
=
-6.2 A
0.025 0.024
V
GS
=
-1.8 V, I
D
=
-5.2 A
0.030 0.030
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
-1.5 V, I
D
=
-3 A
0.035 0.036
Forward Transconductance
a
g
fs
V
DS
=
-5 V, I
D
=
-7 A
25 25 S
Diode Forward Voltage
a
V
SD
I
S
=
-1.7 A, V
GS
= 0 V
-0.83
-0.62
V
Dynamic
b
Total Gate Charge
Q
g
22
25
Gate-Source Charge
Q
gs
2.5
2.5
Gate-Drain Charge
Q
gd
V
DS
=
-10 V, V
GS
=
-4.5 V, I
D
=
-7 A
7 7
nC
Notes
a. Pulse test; pulse width
300 µs, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
2
www.vishay.com
Document Number: 73150
S-50836
Rev. B, 16-May-05
Vishay Siliconix
SPICE Device Model Si3495DV
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
°C UNLESS OTHERWISE NOTED)
3
www.vishay.com
Document Number: 73150
S-50836
Rev. B, 16-May-05
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