(6,6 mm x 6,4 mm)

(4,15 mm x 4,15 mm)

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FEATURES

APPLICATIONS

TYPICAL APPLICATION

OFF

VBAT

LBI

SKIPEN

ADEN

ENPB

LDOEN

SWN

VOUT

PGOOD

LBO1

LBO2

LDOIN

LDOOUT

LDOSENSE

GND

PGND

Control

Inputs

Control
Outputs

CC1

CC2

TPS61100

Battery

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

DUAL-OUTPUT, SINGLE-CELL BOOST CONVERTER

Low EMI-Converter (Integrated Antiringing
Switch)

Synchronous 95% Efficient Boost Converter

Load Disconnect During Shutdown

Integrated 120 mA LDO for Second Output

Auto Discharge Allows the Device to

Voltage

Discharge Output Capacitor During Shutdown

TSSOP-20 and QFN-24 Package

Overtemperature Protection

65 µA (Typ) Total Device Quiescent Current

EVM Available (TPS6110XEVM-216)

0.8 V to 3.3 V Input Voltage Range

Adjustable Output Voltage up to 5.5 V and
Fixed Output Voltage Options

All Single or Dual Cell Battery Operated
Products Which Use Two System Voltages

Power-Save Mode for Improved Efficiency at

Like DSP C5X Applications

Low Output Power

Internet Audio Player, PDAs, Digital Still

Battery Supervision

Cameras and Other Portable Equipment

Power Good Output

Pushbutton Function for Start-Up

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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DESCRIPTION

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The TPS6110x devices provide a complete power supply solution for products powered by either one or two
Alkaline, NiCd, or NiMH battery cells. The converter generates two stable output voltages that are either adjusted
by an external resistor divider or fixed internally on the chip. It stays in operation with supply voltages down to
0.8 V. The implemented boost converter is based on a fixed frequency, pulse-width-modulation (PWM) controller
using a synchronous rectifier to obtain maximum efficiency.

The maximum peak current in the boost switch is limited to a value of 1800 mA.

The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnected
from the battery. An auto discharge function allows discharging the output capacitors during shutdown mode.
This is especially useful in microcontroller applications where the microcontroller or microprocessor should not
remain active due to the stored voltage on the output capacitors. Programming the ADEN-pin disables this
feature. A low-EMI mode is implemented to reduce ringing and in effect lower radiated electromagnetic energy
when the converter enters the discontinuous conduction mode. A power good output at the boost stage provides
additional control of cascaded power supply components.

The built-in LDO can be used for a second output voltage derived either from the boost output or directly from
the battery. The output voltage of this LDO can be programmed by an external resistor divider or is fixed
internally on the chip. The LDO can be enabled separately i.e., using the power good of the boost stage.

The device is packaged in a 20-pin TSSOP (20 PW) package or in a 24-pin QFN (24 RGE) package.

AVAILABLE PACKAGE OPTIONS

PACKAGE

CODE

20-Pin TSSOP

24-Pin QFN

RGE

AVAILABLE OUTPUT VOLTAGE OPTIONS

OUTPUT

VOLTAGE

PART NUMBER

(1)

PART NUMBER

(1)

DC/DC

LDO

Adjustable

TPS61100PW

TPS61100RGE

3.3 V

Adjustable

TPS61103PW

TPS61103RGE

C to 85

3.3 V

1.5 V

TPS61106PW

TPS61106RGE

3.3 V

1.8 V

TPS61107PW

TPS61107RGE

(1)

The PW package is available taped and reeled. Add R suffix to device type (e.g., TPS61100PWR) to
order quantities of 2000 devices per reel. The RGE package is only available in reels. Add R suffix to
device type (e.g. TPS61100RGER) to order quantities of 3000 devices per reel.

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VBAT

LBI

ENPB

ADEN

LDOSENSE

LDOEN

LDOIN

LDOOUT

GND

FB
VOUT
SKIPEN
NC
SWN
PGOOD
SWN
LBO2
LBO1
PGND

PW PACKAGE

(TOP VIEW)

VBA

LBI

ENPB

ADEN

LDOIN

LDOEN

LDOSENSE

LBO2

SWN

PGOOD
SWN

SKIPEN

VOUT

TPS6110X

LDOOUT

GND

LBO1

PGND

SWN

VOUT

RGE PACKAGE

(TOP VIEW)

NC No internal connection

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

RGE

ADEN

Auto discharge enable (1/VBAT enabled, 0/GND disabled)

Boost-enable input. (1/VBAT enabled, 0/GND disabled)

ENPB

Boost-enable input (pushbutton). (0/GND enabled. 1/VBAT disabled)

Boost-voltage feedback of adjustable versions

GND

I/O

Control/logic ground

LBI

Low battery comparator input (comparator enabled with EN)

LBO1

Low battery comparator output 1 (open drain)

LBO2

Low battery comparator output 2 (open drain)

LDOEN

LDO-enable input (1/VBAT enabled, 0/GND disabled)

LDOOUT

LDO output

LDOIN

LDO input

LDOSENSE

LDO feedback for voltage adjustment, must be connected to LDOOUT at fixed output voltage
versions

No connection

PGND

9, 10

I/O

Power ground

PGOOD

Boost output power good (1 : good, 0 : failure) (open drain)

SKIPEN

Enable/disable Power save mode (1: VBAT enabled, 0: GND disabled)

SWN

14, 16

13, 14,

Boost switch input

16, 17

VBAT

Supply pin

VOUT

19, 20

Boost output

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DETAILED DESCRIPTION

SYNCHRONOUS RECTIFIER

CONTROLLER CIRCUIT

DEVICE ENABLE

LDO ENABLE

POWER GOOD

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.
Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power
conversion efficiency reaches 95%. To avoid ground shift due to the high currents in the NMOS switch, two
separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS
switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND
pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In
conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in
shutdown and allows current flowing from the battery to the output. This device however uses a special circuit
which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when
the regulator is not enabled (EN = low).

The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of
the converter. No additional components have to be added to the design to make sure that the battery is
disconnected from the output of the converter.

The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input
voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So
changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect
and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,
only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output
voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to
generate an accurate and stable output voltage.

The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and
the inductor. The nominal peak current limit is set to 1500 mA.

An internal temperature sensor prevents the device from getting overheated in case of excessive power
dissipation.

The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. It
also can be enabled with a low signal on ENPB. This forces the converter to start up as long as the low signal is
applied. During this time EN must be set high to prevent the converter from going down into shutdown mode
again. If EN is high, a negative signal on ENPB is ignored.

In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator
is switched off, and the load is isolated from the input (as described in the synchronous rectifier section). This
also means that the output voltage can drop below the input voltage during shutdown. During start-up of the
converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the
battery.

An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than
approximately 0.7 V. When in operation and the battery is being discharged, the device automatically enters the
shutdown mode if the voltage on VBAT drops below approximately 0.7 V. This undervoltage lockout function is
implemented in order to prevent the malfunctioning of the converter.

When the voltage is applied at VBAT, the LDO can be separately enabled and disabled by using the LDOEN pin
in the same way as the EN pin at the dc/dc converter stage described above.

The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a defined
voltage window. So it can be used to enable the converter after pushbutton start-up, or to enable any connected
circuitry such as cascaded converters (LDO) or processor circuits.

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POWER SAVE MODE

AUTO DISCHARGE

LOW BATTERY DETECTOR CIRCUIT--LBI/LBO

LOW-EMI SWITCH

LDO

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

DETAILED DESCRIPTION (continued)

The SKIPEN pin can be used to select different operation modes. To enable power save, SKIPEN must be set
high. Power save mode is used to improve efficiency at light load. In power save mode the converter only
operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or
several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage.
This power save mode can be disabled by setting the SKIPEN to GND.

The auto discharge function is needed in applications where the supply voltage of a microcontroller,
microprocessor or memory has to be removed during shutdown in order to make sure that the system quickly
goes in a defined state. The auto discharge function is enabled when the ADEN is set high. It is disabled when
the ADEN is set to GND. When the auto discharge function is enabled, the output capacitor is discharged after
the device is programmed in the shutdown mode. The output capacitor is discharged by an integrated switch of
400

, hence the discharge time depends on the size of the output capacitor.

The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag
when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is
enabled. When the device is disabled, both LBO-pin are high-impedance. There are three programmed
thresholds, 400 mV, 450 mV, and 500 mV. The outputs on LBO1 and LBO2 are shown as follows:

LBI INPUT

LBO1

LBO2

(mV)

0-400

400-450

450-500

500-VBAT

1 means that the output stays at high-impedance and 0 means that the output goes active low. If there is only
one LBO output needed, both outputs can be tied together. Then the switching threshold is at 500 mV at LBI.

The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider
connected to the LBI-pin. The resistive divider scales down the battery voltage to a voltage level of 400 mV
(450 mV, 500 mV), which is then compared to the LBI threshold voltage. The LBI-pin has a built-in hysteresis of
10 mV. See the application section for more details about the programming of the LBI-threshold. If the
low-battery detection circuit is not used, the LBI-pin should be connected to GND (or to VBAT) and the LBO-pin
can be left unconnected. Do not let the LBI-pin float.

The device integrates a circuit that removes the ringing that typically appears on the SW-node when the
converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the
rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the
battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the
inductor, a ringing on the SW-pin is induced. The integrated antiringing switch clamps this voltage to VBAT and
therefore dampens ringing.

The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, from
the battery, or from another power source like an ac adapter or a USB power rail. The LDOSENSE input must be
connected to LDOOUT at fixed output voltage versions.

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ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

over operating free-air temperature range (unless otherwise noted)

UNIT

Input voltage range on VBAT, LBI, SKIPEN, EN, ENPB, ADEN, FB, LDOEN

-0.3 V to 3.6 V

Input voltage range on SWN, VOUT, LDOIN, LDOOUT, LDOSENSE, PGOOD, LBO1, LBO2

-0.3 V to 7 V

Operating free air temperature range, T

-40

C to 85

Maximum junction temperature, T

150

Storage temperature range, T

stg

-65

C to 150

Lead temperature 1,6 mm (1/16 inch) from case for 10s

260

(1)

Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN NOM

MAX

UNIT

Supply voltage at VBAT

0.8

3.3

Boost--inductor

4.7

µH

Boost--input capacitor

µF

Boost--output capacitor

100

µF

LDO--input capacitor

µF

LDO--output capacitor

2.2

µF

Operating virtual junction temperature

-40

125

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ELECTRICAL CHARACTERISTICS

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25

C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BOOST STAGE

Input voltage for start-up

> = 66

at V

= 3.3 V

0.85

1.1

I(b)

Input voltage once started

0.8

3.3

o(b)

Output voltage

1.5

5.5

Minimum possible output power

PW package, VBAT

1.5 V

600

ref

Reference voltage

485

500

515

Oscillator frequency

320

500

800

kHz

Switch current limit

= 3.3 V

1200

1500

1800

Startup current limit

610

Boost switch on resistance

= 3.3 V

180

300

Sync switch on resistance

= 3.3 V

180

300

Total accuracy

-3%

Auto discharge switch resistance

400

VBAT

= 0 mA, V

= VBAT = 3.3 V, V

= 3.3 V, ENLDO = 0

µA

Boost quiescent current

VOUT

= 0 mA, V

= VBAT = 3.3 V, V

= 3.3 V, ENLDO = 0

µA

Boost shutdown current

= 0 V

0.5

µA

LDO STAGE

I(LDO)

Input voltage range

1.5

o(LDO)

Output voltage

0.9

3.6

1.8 V

120

270

o(LDO)

Output current

< 1.8 V

LDO short circuit current limit

500

Minimum voltage drop

1.8 V, I

o(LDO)

= 120 mA

300

Total accuracy

1 mA

Line regulation

LDOIN change form 1.8 V to 2.6 V at 100 mA

0.6%

Load regulation

Load change from 10% to 90%

0.6%

Auto discharge switch resistance

400

LDOIN

LDO quiescent current

LDOIN = 7 V, VBAT = 1.2 V, EN = 0

µA

VBAT

LDO shutdown current

0.01

µA

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ELECTRICAL CHARACTERISTICS (CONTINUED)

PARAMETER MEASUREMENT INFORMATION

SWN

Power

Supply

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS6110x

List of Components:
U1 = TPS6110x
L1 = SUMIDA CDRH74100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum

CC1

Boost Output

CC2

LDO Output

Control
Outputs

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25

C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL STAGE

LBI1 voltage threshold

LBI

voltage decreasing

390

400

410

LBI2 voltage threshold

LBI

voltage decreasing

440

450

460

LBI3 voltage threshold

LBI

voltage decreasing

490

500

510

LBI input hysteresis

LBI input current

EN = Vbat or GND

0.01

0.1

µA

LBO1 output low voltage

= 3.3 V, I

= 10 µA

0.04

0.4

LBO1 output low current

µA

LBO1 output leakage current

LBO

= 3.3 V

0.01

0.1

µA

LBO2 output low voltage

= 3.3 V, I

= 10 µA

0.04

0.4

LBO2 output low current

µA

LBO2 output leakage current

LBO

= 3.3 V

0.01

0.1

µA

EN, ENPB, LDOEN, SKIPEN and ADEN input

0.2

VBAT

low voltage

EN, ENPB, LDOEN, SKIPEN and ADEN input

0.8

VBAT

high voltage

EN, ENPB, LDOEN, SKIPEN and ADEN input

Clamped on GND or VBAT

0.01

0.1

µA

current

Powergood threshold

= 3.3 V

0.9xV

0.92xV

0.95xV

Powergood delay

µs

Powergood output low voltage

= 3.3 V, I

= 10 µA

0.04

0.4

Powergood output low current

µA

Powergood output leakage current

0.01

0.1

µA

Overtemperature protection

140

Overtemperature hysteresis

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TYPICAL CHARACTERISTICS

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Table of Graphs

BOOST CONVERTER

Figure

vs Input voltage for VOUT = 3.3 V, 5.0 V

Maximum output current

vs Input voltage for VOUT = 1.8 V, 2.5 V

vs Output current for VIN = 1.2 V, VOUT = 1.5 V

vs Output current for VIN = 1.2 V, VOUT = 2.5 V

vs Output current for VIN = 1.2 V, VOUT = 3.3 V

Efficiency

vs Output current for VIN = 1.8 V, VOUT = 2.5 V

vs Output current for VIN = 2.4 V, VOUT = 3.3 V

vs Output current for VIN = 2.4 V, VOUT = 5.0 V

vs Input voltage for Iout = 10 mA/100 mA/200 mA, VOUT = 3.3 V

Output voltage

vs Output current TPS61103/6

Minimum start-up supply voltage

vs Load resistance

No-load supply current into VBAT

vs Input voltage

No-load supply current into VOUT

vs Input voltage

Output voltage (ripple) in continuous modeInductor current

Output voltage (ripple) in power save modeInductor current

Waveforms

Load transient response for output current step of 40 mA to 120 mA

Line transient response for supply voltage step from 1 V to 1.5 V at Iout = 100 mA

Boost converter start-up after enable

LDO

vs Input voltage for VOUT = 2.5 V, 3.3 V

Maximum output current

vs Input voltage for VOUT = 1.5 V, 1.8 V

Output voltage

vs Output current TPS61106

Dropout voltage

vs Output current TPS61100 at 3.3 V TPS61106

No-load supply current into LDOIN

vs Input voltage

PSRR

vs Frequency

Load transient response for output current step of 20 mA to 100 mA

Waveforms

Line transient response for supply voltage step from 1.8 V to 2.4 V at Iout = 100 mA

LDO start-up after enable

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0.2

0.4

0.6

0.8

1.2

1.4

VI - Input Voltage - V

Maximum Output Current -

= 1.8 V

= 2.5 V

0.8

1.8

1.2

1.4

1.6

2.2

2.4

TPS61100

0.2

0.4

0.6

0.8

1.2

0.8

1.8

VI - Input Voltage - V

= 3.3 V

= 5 V

1.2 1.4 1.6

2 2.2 2.4 2.6 2.8

3.2

TPS61100

Maximum Output Current -

100

0.1

100

1000

Efficiency - %

- Output Current - mA

TPS61100
V

= 1.5 V,

BAT

= 1.2 V

100

0.1

100

1000

Efficiency - %

- Output Current - mA

TPS61100
V

= 2.5 V,

BAT

= 1.2 V

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

MAXIMUM OUTPUT CURRENT

INPUT VOLTAGE

Figure 1.

Figure 2.

EFFICIENCY

OUTPUT CURRENT

Figure 3.

Figure 4.

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100

0.1

100

1000

Efficiency - %

- Output Current - mA

TPS61106
V

BAT

= 1.2 V

100

0.1

100

1000

Efficiency - %

- Output Current - mA

TPS61100
V

= 2.5 V,

BAT

= 1.8 V

100

0.1

100

1000

Efficiency - %

- Output Current - mA

TPS61106
V

BAT

= 2.4 V

100

0.1

100

Efficiency - %

- Output Current - mA

TPS61100
V

= 5 V,

BAT

= 2.4 V

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

OUTPUT CURRENT

Figure 5.

Figure 6.

EFFICIENCY

OUTPUT CURRENT

Figure 7.

Figure 8.

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3.18

3.2

3.22

3.24

3.26

3.28

3.3

3.32

3.34

- Output V

oltage - V

- Output Current - mA

TPS61103/6

VBAT = 1.2 V

0.1

100

1000

100

Efficiency - %

- Input Voltage - V

= 100 mA

= 10 mA

= 250 mA

TPS61106

0.8 1

1.2 1.4 1.6 1.8 2

2.2 2.4 2.6 2.8

3.2

0.7

0.75

0.8

0.85

0.9

0.95

100

Minimum Startup Supply V

oltage - V

Load Resistance -

TPS61106

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40

- Input Voltage - V

No-Load Supply Current Into VBA

T -

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

OUTPUT VOLTAGE

INPUT VOLTAGE

OUTPUT CURRENT

Figure 9.

Figure 10.

MINIMUM START-UP SUPPLY VOLTAGE

NO-LOAD SUPPLY CURRENT INTO VBAT

LOAD RESISTANCE

INPUT VOLTAGE

Figure 11.

Figure 12.

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Inductor Current
200 mA/Div, DC

Output Voltage
20 mV/Div, AC

Timebase - 1

s/Div

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

- Input Voltage - V

-40

TPS61106

N0-Load Supply Current Into - VOUT -

Timebase - 500

s/Div

Inductor Current
200 mA/Div, DC

Output Voltage
50 mV/Div, AC

Output Voltage
20 mV/Div, AC

Output Current
50 mA/Div, DC

Timebase - 500

s/Div

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

NO-LOAD SUPPLY CURRENT INTO VOUT

INPUT VOLTAGE

OUTPUT VOLTAGE IN CONTINUOUS MODE

Figure 13.

Figure 14.

OUTPUT VOLTAGE IN POWER SAVE MODE

LOAD TRANSIENT RESPONSE

Figure 15.

Figure 16.

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Output Voltage
50 mV/Div, AC

Input Voltage
500 mV/Div, DC

Timebase - 2 ms/Div

Output Voltage
2 V/Div, DC

Input Current
500 mA/Div, DC

Enable
2 V/Div, DC

Voltage at SW
2 V/Div, DC

Timebase - 400

s/Div

0.1

0.15

0.2

0.25

0.3

0.35

2.5

3.5

4.5

5.5

6.5

= 3.3 V

= 2.5 V

Maximum LDO Output Current -

LDO Input Voltage - V

0.1

0.15

0.2

0.25

0.3

0.35

1.5

2.5

3.5

4.5

5.5

= 1.8 V

= 1.5 V

Maximum LDO Output Current -

LDO Input Voltage - V

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

LINE TRANSIENT RESPONSE

BOOST-CONVERTER START-UP AFTER ENABLE

Figure 17.

Figure 18.

MAXIMUM LDO OUTPUT CURRENT

LDO INPUT VOLTAGE

Figure 19.

Figure 20.

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1.45

1.46

1.47

1.48

1.49

1.5

1.51

100

150

200

LDO Output V

oltage - V

LDO Output Current - mA

TPS61106
LDOIN = 1.8 V

0.5

1.5

2.5

3.5

100

200

300

400

500

TPS61106

(LDO OUTPUT

VOLTAGE 1.5 V)

TPS61100
(LDO OUTPUT
VOLTAGE 3.3 V)

LDO Dropout V

oltage - V

LDO Output Current - mA

10k

100k

10M

PSRR - dB

f - Frequency - Hz

LDO Output Current 10 mA

LDO Output Current 100 mA

TPS61106
LDOIN = 3.3 V

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40

LDOIN Input Voltage - V

Supply Current Into LDOIN -

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

LDO OUTPUT VOLTAGE

LDO DROPOUT VOLTAGE

LDO OUTPUT CURRENT

Figure 21.

Figure 22.

SUPPLY CURRENT INTO LDOIN

PSRR

LDOIN INPUT VOLTAGE

FREQUENCY

Figure 23.

Figure 24.

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APPLICATION INFORMATION

DESIGN PROCEDURE

Programming the Output Voltage

180 k

500 mV

(1)

SWN

Power

Supply

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61100

CC1

Boost Output

CC2

LDO Output

Control
Outputs

180 k

500 mV

(2)

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

The TPS6110x boost converters are intended for systems powered by a single-cell NiCd or NiMH battery with a
typical terminal voltage between 0.9 V and 1.6 V. They can also be used in systems powered by two-cell NiCd or
NiMH batteries with a typical stack voltage between 1.8 V and 3.2 V. Additionally, single- or dual-cell, primary
and secondary alkaline battery cells can be the power source in systems where the TPS6110x is used.

Boost Converter

The output voltage of the TPS61100 boost converter section can be adjusted with an external resistor divider.
The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is
5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB
pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those
two values, the recommended value for R6 should be lower than 500 k

, in order to set the divider current at 1

µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200
k

. From that, the value of resistor R3, depending on the needed output voltage (V

), can be calculated using

Equation 1:

If as an example, an output voltage of 3.3 V is needed, a 1-M

resistor should be chosen for R3.

Figure 28. Typical Application Circuit for Adjustable Output Voltage Option

LDO

Programming the output voltage at the LDO follows almost the same rules as at the boost converter section. The
maximum programmable output voltage at the LDO is 3.3 V. Since reference and internal feedback circuitry are
similar, as they are at the boost converter section, R4 also should be in the 200-k

range. The calculation of the

value of R5 can be done using the following Equation 2:

If as an example, an output voltage of 1.5 V is needed, a 360 k

-resistor should be chosen for R5.

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Programming the LBI/LBO Threshold Voltage

BAT

LBI-threshold

390 k

BAT

450 mV

(3)

BAT

LBI-threshold

R1
R2

)

500 mV

680 k

390 k

)

(4)

Inductor Selection

OUT

BAT

0.8

(5)

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

APPLICATION INFORMATION (continued)

The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The
typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is
generated on-chip, which has a value of 400 mV, 450 mV or 500 mV. The recommended value for R2is therefore
in the range of 500 k

. From that, the value of resistor R

, depending on the desired minimum battery voltage

BAT,

can be calculated using Equation 3.

For example, if the low-battery detection circuit should flag an error condition for the 450 mV threshold on the
LBO outputs at a battery voltage of 1.23 V, a 680-k

resistor should be chosen for R1. The resulting battery

voltages of the other thresholds can be calculated using Equation 4:

The result for the 500-mV threshold in our example is 1.37 V and for the 400-mV threshold 1.1 V. This results in
the following truth table for the battery supervisor outputs:

VBAT [V]

LBO1

LBO2

0-1.1

1.1-1.23

1.23-1.37

1.37-VBAT max

If the application requires only a simple LBI/LBO function both LBO outputs can be connected together. The LBI
threshold then is 500 mV.

The outputs of the low battery supervisor are simple open-drain outputs that go active low if the dedicated battery
voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a
recommended value of 1 M

. The maximum voltage which is used to pull up the LBO outputs should not exceed

the output voltage of the boost converter. If not used, the LBO pin can be left floating or tied to GND.

A boost converter normally requires two main passive components for storing energy during the conversion. A
boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is
recommended to keep the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. For example, the current limit threshold of the TPS6110x's switch is 1200 mA at an
output voltage of 3.3 V. The highest peak current through the inductor and the switch depends on the output
load, the input (V

BAT

), and the output voltage (V

OUT

). Estimation of the maximum average inductor current can be

done using Equation 5:

For example, for an output current of 100 mA at 3.3 V, at least 515 mA of current flows through the inductor at a
minimum input voltage of 0.8 V.

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BAT

OUT

BAT

OUT

(6)

CAPACITOR SELECTION

Input Capacitor

Output Capacitor Boost Converter

min

OUT

BAT

OUT

(7)

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those
parameters, it is possible to calculate the value for the inductor by using Equation 6:

Parameter 0 is the switching frequency and

is the ripple current in the inductor, i.e., 20%

. In this example,

the desired inductor has the value of 12 µH. With this calculated value and the calculated currents, it is possible
to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to
higher currents as estimated in Equation 5. Also, the losses in the inductor caused by magnetic hysteresis losses
and copper losses are a major parameter for total circuit efficiency.

Table 1. Inductors

VENDOR

RECOMMENDED INDUCTOR SERIES

CDRH73

CDRH74

Sumida

CDRH5D18

CDRH6D38

DR73

Coiltronics

DR74

LQS66C

Murata

LQN6C

SLF 7045

TDK

SLF 7032

WE-PD Type M

Wurth Electronic

WE-PD Type S

At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.

The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 7:

Parameter f is the switching frequency and

V is the maximum allowed ripple.

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ESR

OUT

ESR

(8)

Output Capacitor LDO

LAYOUT CONSIDERATIONS

APPLICATION EXAMPLES

SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61106

List of Components:
U1 = TPS61106
L1 = SUMIDA CDRH74100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum

3.3 V,
>250 mA

2.2

1.5 V,
>120 mA

LBO1

LBO2

PGOOD

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

With a chosen ripple voltage of 15 mV, a minimum capacitance of 10 µF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 8:

An additional ripple of 10 mV is the result of using a tantalum capacitor with a low ESR of 100 m

. The total

ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In
this example, the total ripple is 25 mV. It is possible to improve the design by enlarging the capacitor or using
smaller capacitors in parallel to reduce the ESR or by using better capacitors with lower ESR, like ceramics. So,
trade-offs have to be made between performance and costs of the converter circuit.

To ensure stable output regulation, it is required to use an output capacitor at the LDO output. We recommend
using ceramic capacitors in the range from 1 µF up to 4.7 µF. At 4.7 µF and above it is recommended to use
standard ESR tantalum. There is no maximum capacitance value.

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.

Figure 29. Solution for Maximum Output Power

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SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61106

List of Components:
U1 = TPS61106
L1 = SUMIDA 5D18100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR, Low Profile Tantalum

3.3 V

2.2

1.5 V

LBO1

LBO2

PGOOD

SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61106

List of Components:
U1 = TPS61106
L1 = SUMIDA CDRH74100
C3, C5, C6,
C7, C8 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
DS1 = BAT54S

3.3 V

2.2

1.5 V

LBO1

LBO2

PGOOD

0.1

DS1

6 V

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Figure 30. Low Profile Solution, Maximum Height 1,8 mm

Figure 31. Dual Power Supply With Auxiliary Positive Output Voltage

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SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61106

List of Components:
U1 = TPS61106
L1 = SUMIDA CDRH74100
C3, C5, C6,
C7, C8 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
DS1 = BAT54S

3.3 V

2.2

1.5 V

LBO1

LBO2

PGOOD

0.1

DS1

3 V

SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61100

List of Components:
U1 = TPS61100
L1 = SUMIDA CDRH74100
C3, C5 = X7R/X5R Ceramic
C6 = X7R/X5R Ceramic or Low
ESR Tantalum

3.3 V

LBO1

LBO2

PGOOD

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Figure 32. Dual Power Supply With Auxiliary Negative Output Voltage

Figure 33. Single Output Using LDO as Filter

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SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SKIPEN

ADEN
EN

ENPB

LDOEN

GND

TPS61106

List of Components:
U1 = TPS61106
L1 = SUMIDA 5D18100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum

3.3 V

2.2

1.5 V

LBO1

LBO2

R10

SWN

USB-Input

4.2 V 5.5 V

VBAT

VOUT

R3 1 M

180 k

LDOIN

R5 1.022 M

180 k

LDOSENSE

LDOOUT

2.2

100

LBO1

LBO2

PGOOD

PGND

LBI

SYNC

ADEN
EN

ENPB

LDOEN

GND

TPS61100

3.3 V System
Supply

Control
Outputs

R10
680 k

R11
1 M

R12
180 k

List of Components:
U1 = TPS61100
L1 = SUMIDA CDRH73100
C3, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
D1 = ON-Semiconductor MBR0520

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Figure 34. Simple Solution Using a Pushbutton for Start-Up

Figure 35. Dual Input Power Supply

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SWN

VBAT

VOUT

LDOIN

LDOSENSE

LDOOUT

2.2

100

LBO1
LBO2

PGOOD

PGND

LBI

SKIPEN
ADEN

ENPB

LDOEN

GND

TPS6110XRGE

2.2

LBO1
LBO2
PGOOD

LDOOUT

OUTPUT

LDOEN

ENPB

ADEN

SKIPEN

INPUT

R11

R10

THERMAL INFORMATION

D(MAX)

J(MAX)

150

155 k W

420 mW

(9)

TPS61100, TPS61103
TPS61106, TPS61107

SLVS411B JUNE 2002 REVISED APRIL 2004

Figure 36. TPS6110x EVM Circuit Diagram

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

Improving the power dissipation capability of the PCB design.

Improving the thermal coupling of the component to the PCB.

Introducing airflow in the system.

The maximum junction temperature (T

) of the TPS6110x devices is 150

C. The thermal resistance of the 20-pin

TSSOP package (PW) isR

= 155 K/W (QFN package, RGE, 161 K/W). Specified regulator operation is

assured to a maximum ambient temperature T

of 85

C. Therefore, the maximum power dissipation is about 420

mW. More power can be dissipated if the maximum ambient temperature of the application is lower.

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Part Number TPS61106

Document Outline