TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B DECEMBER 1996 REVISED AUGUST 1997
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
95-m
Maximum (5-V Input) High-Side
MOSFET Switch
D
Short-Circuit Protection and Thermal
Protection
D
Logic Overcurrent Output
D
4-V to 7-V Operating Range
D
Enable Input Compatible With 3-V and 5-V
Logic
D
Controlled Rise and Fall Times Limit
Current Surges and Minimize EMI
D
Undervoltage Lockout Ensures That Switch
is Off at Start-Up
D
10-
µ
A Maximum Standby Current
D
Available in Space-Saving 8-Pin SOIC and
8-Pin PDIP
D
0
°
C to 125
°
C Operating Junction
Temperature Range
D
12-kV Output, 6-kV Input Electrostatic-
Discharge Protection
description
The TPS2014 and TPS2015 power distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. The high-side switch is a 95-m
n-channel MOSFET. The
switch is controlled by a logic enable that is compatible with 3-V and 5-V logic. Gate drive is provided by an
internal charge pump designed to control the power switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 4 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS20xx limits the output
current to a safe level by switching into a constant-current mode, and the overcurrent logic output is set to low.
Continuous heavy overloads and short circuits will increase the power dissipation in the switch and cause the
junction temperature to rise. A thermal protection circuit is implemented, which shuts the switch off to prevent
damage when the junction temperature exceeds its thermal limit. An undervoltage lockout is provided to ensure
the switch is in the off state at start-up.
The TPS2014 and TPS2015 differ only in short-circuit current limits. The TPS2014 is designed to limit at 1.2 A
load and the TPS2015 limits at 2 A (see the available options table). The TPS20xx is available in 8-pin
small-outline integrated circuit (SOIC) and 8-pin PDIP packages, and operates over a junction temperature
range of 0
°
C to 125
°
C.
AVAILABLE OPTIONS
RECOMMENDED MAXIMUM
TYPICAL SHORT CIRCUIT
PACKAGED DEVICES
CHIP FORM
TA
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25
°
C
SOIC
(D)
PDIP
(P)
CHIP FORM
(Y)
0
°
C TO 85
°
C
0.6 A
1.2 A
TPS2014D
TPS2014P
TPS2014Y
0
°
C TO 85
°
C
1 A
2 A
TPS2015D
TPS2015P
TPS2015Y
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2014DR).
Copyright
©
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
D OR P PACKAGE
(TOP VIEW)
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B DECEMBER 1996 REVISED AUGUST 1997
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
Current Sense
TPS20xxY chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS20xx. Ultrasonic
bonding may be used on the doped aluminium bonding pads. The chip may be mounted with conductive epoxy
or a gold-silicon preform.
91
74
CHIP THICKNESS: 15 TYPICAl
BONDING PADS: 4
×
4 MINIMUM
TJ max = 150
°
C
TOLERANCES ARE
±
10%.
ALL DIMENSIONS ARE IN MILS.
OUT
OUT
OUT
OC
GND
IN
IN
EN
TPS20xxY
(1)
(2)
(3)
(4)
(8)
(7)
(6)
(5)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
BONDING PAD ASSIGNMENTS
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B DECEMBER 1996 REVISED AUGUST 1997
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Enable input. Logic low at EN turns the power switch on.
GND
1
I
Ground
IN
2, 3
I
Input voltage
OC
5
O
OC is asserted active low during a fault condition.
OUT
68
O
Power switch output
detailed description
power switch
The power switch is an n-channel MOSFET with a maximum on-state resistance of 95 m
(V
I(IN)
= 5 V),
configured as a high-side switch.
charge pump
An internal 100-kHz charge pump supplies power to the driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 4 V and
requires very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the
microsecond or nanosecond range for a standard FET.
enable (EN)
A logic high on EN turns off the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current to less than 10
µ
A. A logic zero input restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OC)
OC is an open-drain logic output that is asserted (active low) when an overload or short circuit is encountered.
The output remains asserted until the overload or short-circuit condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET provides a much more efficient way to
measure current than conventional resistance methods. When an overload or short circuit is encountered, the
current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives
the power FET into its linear region, which switches the output into a constant current mode and simply holds
the current constant while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately to 180
°
C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20
°
C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
An internal voltage sense monitors the input voltage. When the input voltage is below 3.2 V nominal, a control
signal turns off the power switch.
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B DECEMBER 1996 REVISED AUGUST 1997
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V
I
(see Note1)
0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note1)
0.3 V to V
I(IN)
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
at EN
0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
internally
limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
0
°
C to 125
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA
25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 70
°
C
POWER RATING
TA = 125
°
C
POWER RATING
P
1175 mW
9.4 mW/
°
C
752 mW
235 mW
D
725 mW
5.8 mW/
°
C
464 mW
145 mW
recommended operating conditions
MIN
MAX
UNIT
Input voltage, VI
4
5.5
V
Input voltage, VI at EN
0
5.5
V
Continuous output current IO
TPS2014
0
0.6
A
Continuous output current, IO
TPS2015
0
1
A
Operating virtual junction temperature, TJ
0
125
°
C
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, EN = 0 V (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI = 5.5 V,
TJ = 25
°
C
75
95
r
On state resistance
VI = 5 V,
TJ = 25
°
C
80
95
m
ron
On-state resistance
VI = 4.5V,
TJ = 25
°
C
90
110
m
VI = 4 V,
TJ = 25
°
C
96
110
Ilk
Leakage current output
EN = VI,
TJ = 25
°
C
0.001
1
µ
A
Ilkg
Leakage current, output
EN = VI,
0
°
C
TJ
125
°
C
10
µ
A
t
Rise time output
VI = 5.5 V,
TJ = 25
°
C
CL = 1
µ
F
4
ms
tr
Rise time, output
VI = 4 V,
TJ = 25
°
C
CL = 1
µ
F
3.8
ms
tf
Fall time output
VI = 5.5 V,
TJ = 25
°
C
CL = 1
µ
F
3.9
ms
tf
Fall time, output
VI = 4 V,
TJ = 25
°
C
CL = 1
µ
F
3.5
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B DECEMBER 1996 REVISED AUGUST 1997
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, EN = 0 V (unless otherwise noted) (continued)
enable input (EN)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VIH
High-level input voltage
4 V
VI
5.5 V
2
V
VIL
Low-level input voltage
4 V
VI
5.5 V
0.8
V
II
Input current
EN = 0 V or EN = VI
0.5
0.5
µ
A
tPLH Propagation (delay) time, low to high output
CL = 1
µ
F
20
ms
tPHL Propagation (delay) time, high to low output
CL = 1
µ
F
40
ms
current limit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOS
Short circuit output current
TJ = 25
°
C VI = 5 5 V
TPS2014
0.66
1.2
1.8
A
IOS
Short-circuit output current
TJ = 25
°
C, VI = 5.5 V
TPS2015
1.1
2
3
A
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
supply current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDDL
Supply current low level output
EN
VI
TJ = 25
°
C
0.015
10
µ
A
IDDL
Supply current, low-level output
EN = VI
0
°
C
TJ
125
°
C
10
µ
A
IDDH
Supply current high level output
EN = 0 V
TJ = 25
°
C
73
100
µ
A
IDDH
Supply current, high-level output
EN = 0 V
0
°
C
TJ
125
°
C
100
µ
A
undervoltage lockout
PARAMETER
MIN
TYP
MAX
UNIT
VIL
Low-level input voltage
2
3.2
4
V
OC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOS
Short-circuit output current
0
°
C
TJ
125
°
C
5
mA
VOL
Low-level output voltage
0
°
C
TJ
125
°
C
0.3
mA
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