TPIC5322L
3-CHANNEL INDEPENDENT LOGIC-LEVEL POWER DMOS ARRAY
SLIS034A JUNE 1994 REVISED NOVEMBER 1994
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Low r
DS(on)
. . . 0.45
Typ
D
High-Voltage Outputs . . . 60 V
D
Pulsed Current . . . 3 A Per Channel
D
Fast Commutation Speed
D
Direct Logic-Level Interface
description
The TPIC5322L is a monolithic logic-level power
DMOS array that consists of three electrically
isolated independent N-channel enhancement-
mode DMOS transistors.
The TPIC5322L is offered in a standard 16-pin
small-outline surface-mount (D) package and is
characterized for operation over the case
temperature range of 40
°
C to 125
°
C.
schematic
GATE1
DRAIN1
8
11
Q1
Q2
Q3
9, 10
12, 13
15, 16
Z1
Z2
Z3
SOURCE2
DRAIN2
DRAIN3
GATE2
GATE3
D1
D2
D3
SOURCE1
2, 3
14
GND
1
4, 5
6, 7
SOURCE3
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
DS
60 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage
100 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-GND voltage
100 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage, V
GS
±
20 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, T
C
= 25
°
C 1
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current, T
C
= 25
°
C 1
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
, T
C
= 25
°
C (see Note 1 and Figure 15)
3 A
. . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, E
AS
, T
C
= 25
°
C (see Figure 4)
40.5 mJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) T
C
= 25
°
C 1.09
W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
40
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
40
°
C to 125
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%.
Copyright
©
1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SOURCE1
SOURCE1
SOURCE2
SOURCE2
SOURCE3
SOURCE3
GATE3
DRAIN1
DRAIN1
GATE1
DRAIN2
DRAIN2
GATE2
DRAIN3
DRAIN3
D PACKAGE
(TOP VIEW)
TPIC5322L
3-CHANNEL INDEPENDENT LOGIC-LEVEL POWER DMOS ARRAY
SLIS034A JUNE 1994 REVISED NOVEMBER 1994
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics, T
C
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(BR)DSX
Drain-to-source breakdown voltage
ID = 250
µ
A,
VGS = 0
60
V
VGS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 5
VDS = VGS,
1.5
1.85
2.2
V
V(BR)
Reverse drain-to-GND breakdown voltage (across
D1, D2, and D3)
Drain-to-GND current = 250
µ
A
100
V
VDS(on)
Drain-to-source on-state voltage
ID = 1 A,
See Notes 2 and 3
VGS = 5 V,
0.45
0.525
V
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1 A,
VGS = 0,
See Notes 2 and 3 and Figure 12
0.85
1
V
VF
Forward on-state voltage, GND-to-drain
ID = 1 A
3.7
V
IDSS
Zero gate voltage drain current
VDS = 48 V,
TC = 25
°
C
0.05
1
µ
A
IDSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125
°
C
0.5
10
µ
A
IGSSF
Forward gate current, drain short circuited to
source
VGS = 16 V,
VDS = 0
10
100
nA
IGSSR
Reverse gate current, drain short circuited to
source
VSG = 16 V,
VDS = 0
10
100
nA
Ilk
Leakage current drain to GND
VDGND = 48 V
TC = 25
°
C
0.05
1
µ
A
Ilkg
Leakage current, drain-to-GND
VDGND = 48 V
TC = 125
°
C
0.5
10
µ
A
rDS( )
Static drain to source on state resistance
VGS = 5 V,
ID = 1 A,
TC = 25
°
C
0.45
0.525
rDS(on)
Static drain-to-source on-state resistance
D
,
See Notes 2 and 3
and Figures 6 and 7
TC = 125
°
C
0.7
0.78
gfs
Forward transconductance
VDS = 10 V,
ID = 0.5 A,
See Notes 2 and 3 and Figure 9
1
1.24
S
Ciss
Short-circuit input capacitance, common source
135
170
Coss
Short-circuit output capacitance, common source
VDS = 25 V,
VGS = 0,
80
100
pF
Crss
Short-circuit reverse-transfer capacitance,
common source
f = 1 MHz,
See Figure 11
30
40
F
NOTES:
2. Technique should limit TJ TC to 10
°
C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T
C
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Reverse recovery time
Z1, Z2, Z3
35
ns
trr
Reverse-recovery time
IS = 0.5 A,
VGS = 0
VDS = 48 V,
di/dt = 100 A /
µ
s
D1, D2, D3
110
ns
QRR
Total diode charge
VGS = 0,
See Figures 1 and 14
di/dt = 100 A /
µ
s,
Z1, Z2,Z3
0.035
µ
C
QRR
Total diode charge
See Figures 1 and 14
D1, D2, D2
0.35
µ
C
TPIC5322L
3-CHANNEL INDEPENDENT LOGIC-LEVEL POWER DMOS ARRAY
SLIS034A JUNE 1994 REVISED NOVEMBER 1994
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
resistive-load switching characteristics, T
C
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(on)
Turn-on delay time
21
42
td(off)
Turn-off delay time
VDD = 25 V,
RL = 50
,
ten = 10 ns,
20
40
ns
tr
Rise time
DD
,
tdis = 10 ns,
L
,
See Figure 2
en
,
5
10
ns
tf
Fall time
13
26
Qg
Total gate charge
V
48 V
I
0 5 A
V
5 V
3.1
3.8
Qgs(th) Threshold gate-to-source charge
VDS = 48 V,
See Figure 3
ID = 0.5 A,
VGS = 5 V,
0.4
0.5
nC
Qgd
Gate-to-drain charge
See Figure 3
1.3
1.6
LD
Internal drain inductance
5
nH
LS
Internal source inductance
5
nH
Rg
Internal gate resistance
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
JA
Junction-to-ambient thermal resistance
(see Note 4)
All outputs with equal power
115
°
C/W
R
JP
Junction-to-pin thermal resistance
q
32
°
C/W
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink
PARAMETER MEASUREMENT INFORMATION
t Time ns
0
25
50
75
100
125
150
175
200
225
250
1
0.5
0
0.5
1
1.5
2
2.5
3
Source-to-Drain Diode Current
A
I S
trr(SD)
IRM
25% of IRM
VDS = 48 V
VGS = 0
TJ = 25
°
C
Z1, Z2, and Z3
Shaded Area = QRR
Reverse di/dt = 100 A/
µ
s
IRM = maximum recovery current
NOTE A: The above waveform is representative of D1, D2, and D3 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
TPIC5322L
3-CHANNEL INDEPENDENT LOGIC-LEVEL POWER DMOS ARRAY
SLIS034A JUNE 1994 REVISED NOVEMBER 1994
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Pulse Generator
50
Rgen
50
VGS
VDD = 25 V
DUT
VDS
TEST CIRCUIT
VDD
VDS(on)
tf
td(on)
tr
td(off)
VOLTAGE WAVEFORMS
VGS
VDS
RL
CL = 30 pF
(see Note A)
tdis
ten
5 V
0
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Qg
5 V
VOLTAGE WAVEFORM
Qgd
Time
Gate Voltage
VGS
12-V
Battery
0.2
µ
F
50 k
0.3
µ
F
Current
Regulator
DUT
Same Type
as DUT
0
IG = 1
µ
A
IG Current-
Sampling Resistor
ID Current-
Sampling Resistor
VDD
TEST CIRCUIT
Qgs(th)
VDS
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
TPIC5322L
3-CHANNEL INDEPENDENT LOGIC-LEVEL POWER DMOS ARRAY
SLIS034A JUNE 1994 REVISED NOVEMBER 1994
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
5.25 mH
ID
tw
tav
IAS
V(BR)DSX = 60 V Min
VOLTAGE AND CURRENT WAVEFORMS
0
0
0
ID
VDS
DUT
VDS
TEST CIRCUIT
(see Note A)
(see Note B)
Pulse Generator
50
Rgen
50
VGS
VGS
5 V
NOTES: A. The pulse generator has the following characteristics: tr
10 ns, tf
10 ns, ZO = 50
.
B. Input pulse duration (tw) is increased until peak current IAS = 3 A.
Energy test level is defined as E
AS
+
I
AS
V
(BR)DSX
tav
2
+
40.5 mJ.
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
Figure 5
1
0.5
0
0
20
40
60
80
Gate-to-Source Threshold V
oltage V
1.5
2
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
100 120 140 160
40 20
ID = 1 mA
ID = 100
µ
A
TJ Junction Temperature
°
C
V
GS(th)
VDS = VGS
Figure 6
0.4
0.2
0
0
20
40
60
80
Static Drain-to-Source
0.6
0.8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
1
100 120 140 160
40 20
TJ Junction Temperature
°
C
r
DS(on)
On-State Resistance
ID = 1 A
VGS = 5 V
VGS = 4.5 V
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