TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F DECEMBER 1986 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

CMOS/EEPROM/EPROM Technologies on a
Single Device
Mask-ROM Devices for High-Volume

Production

 One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

 Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations
On-Chip Program Memory Versions

ROM: 4K to 48K Bytes
EPROM: 16K to 48K Bytes
ROM-less

Data EEPROM: 256 or 512 Bytes
Static RAM: 256 to 3.5K Bytes
External Memory / Peripheral Wait States
Precoded External Chip-Select Outputs

in Microcomputer Mode

Flexible Operating Features
Low-Power Modes: STANDBY and HALT
Commercial, Industrial, and Automotive

Temperature Ranges

 Clock Options

Divide-by-4 (0.5 MHz 5 MHz SYSCLK)
Divide-by-1 (2 MHz 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

 Supply Voltage (V

): 5 V

10%

Eight-Channel 8-Bit Analog-to-Digital
Converter 1 (ADC1)

Two 16-Bit General-Purpose Timers

On-Chip 24-Bit Watchdog Timer

Two Communication Modules
Serial Communications Interface 1 (SCI1)
Serial Peripheral Interface (SPI)

Flexible Interrupt Handling

TMS370 Series Compatibility

CMOS/Package /TTL-Compatible I / O Pins
64-Pin Plastic and Ceramic Shrink

Dual-In-Line Packages / 44 Bidirectional,
9 Input Pins

 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages / 46 Bidirectional,
9 Input Pins

 All Peripheral Function Pins Are

Software Configurable for Digital I / O

Workstation/PC-Based Development
System
C Compiler and C Source Debugger
Real-Time In-Circuit Emulation
Extensive Breakpoint / Trace Capability
Software Performance Analysis
Multi-Window User Interface
Microcontroller Programmer

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FN / FZ PACKAGE

( TOP VIEW )

SS1

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

AL2/CLKIN

AL1

C3
C4
C5
C6
C7

SPISOMI

SPICLK

SPISIMO

T1IC/CR
T1PWM
T1EVT

9 8 7 6 5 4 3

10
11
12
13
14
15
16

CSE2

OCF

CC2

SS2

CC1

2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

CC3

SS3

CC1

17
18
19
20
21
22
23

24
25
26

60
59
58
57
56
55
54

53
52
51
50
49
48
47

46
45
44

CC2

SS2

A0
A1
A2
A3
A4
A5
A6
A7

T2AEVT

T2AIC2/PWM

INT1
INT2
INT3

D1 / CSH3

D2 / CSH2
D3 / SYSCLK
D4 / R / W
D5 / CSPF
D6/CSH1/EDS
D7/CSE1/WAIT
RESET

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

JN / NM PACKAGE

( TOP VIEW )

8
9

SS1

AN0

T2AEVT

T2AIC2 / PWM

T2AIC1 / CR

SCICLK

SCIRXD

SCITXD

XTAL2 / CLKIN

XTAL1

CC1

CC3

D0 / CSE2 / OCF

SS1

CC1

D1 / CSH3

D3 / SYSCLK

D4 / R / W

D6 / CSH1 / EDS

D7 / CSE1 / WAIT

RESET

INT1

INT2

INT3

SPISOMI

SPISIMO

SPICLK

T1IC / CR

T1PWM

AN7

T1EVT

SS1

AN6

AN5

AN4

AN3

AN1

AN2

SS3

TMS370Cx5x
8-BIT MICROCONTROLLER

SPNS010F DECEMBER 1986 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Pin Descriptions

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PIN

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁ

NAME

ÁÁÁÁÁÁ

ALTERNATE

FUNCTION

ÁÁÁ

SDIP

(64)

ÁÁÁ

LCC

(68)

ÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

A0
A1
A2
A3
A4
A5
A6
A7

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

ÁÁÁ

15
16
17
18
19
20
21
22

ÁÁÁ

17
18
19
20
21
22
23
24

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port A is a general-purpose bidirectional I/O port.
Expansion mode: Port A can be individually programmed as the external
bidirectional data bus (DATA0 DATA7).

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

B0
B1
B2
B3
B4
B5
B6
B7

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7

ÁÁÁ

60
61
62
63
64

1
2
3

ÁÁÁ

65
66
67
68

1
2
3
4

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port B is a general-purpose bidirectional I/O port.
Expansion mode: Port B can be individually programmed as the low-order address
output bus (ADDR0 ADDR7).

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

C0
C1
C2
C3
C4
C5
C6
C7

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ADDR8
ADDR9

ADDR10

ADDR11

ADDR12
ADDR13
ADDR14
ADDR15

ÁÁÁ

4
6
7
9

12
13

ÁÁÁ

5
7
8

12
13
14

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port C is a general-purpose bidirectional I/O port.
Expansion mode: Port C can be individually programmed as the high-order address
output bus (ADDR8 ADDR15).

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1
INT2
INT3

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

NMI

--
--

ÁÁÁ

50
49
48

ÁÁÁ

52
51
50

ÁÁ

I / O
I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External (nonmaskable or maskable) interrupt/general-purpose input pin
External maskable interrupt input/general-purpose bidirectional pin
External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

E0
E1
E2
E3
E4
E5
E6
E7

ÁÁÁ

14
34
35
36
37
38
39
42

ÁÁÁ

36
37
38
39
40
41
42
43

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ADC1 analog input (AN0 AN7) or positive reference pins (AN1 AN7)
Port E can be individually programmed as general-purpose input pins if not used
as ADC1 analog input or positive reference input.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

VCC3
VSS3

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

32
33

ÁÁÁ

34
35

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ADC1 positive-supply voltage and optional positive-reference input pin
ADC1 ground reference pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

RESET

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System reset bidirectional pin. RESET, as an input, initializes the microcontroller;
as open-drain output, RESET indicates an internal failure was detected by the
watchdog or oscillator fault circuit.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO)
mode, also EPROM VPP.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

XTAL2/CLKIN
XTAL1

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

29
30

ÁÁÁ

31
32

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal oscillator crystal input / external clock source input
Internal oscillator output for crystal

ÁÁÁÁÁ

VCC1

ÁÁÁÁÁÁ

ÁÁÁ

31, 57

ÁÁÁ

33,

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive supply voltage

ÁÁÁÁÁ

VCC2

ÁÁÁÁÁÁ

ÁÁÁ

15,63

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive supply voltage

I = input, O = output
Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F DECEMBER 1986 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Pin Descriptions (Continued)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PIN

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

NAME

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ALTERNATE

FUNCTION

ÁÁÁ

SDIP

(64)

ÁÁÁ

LCC

(68)

ÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ

VSS1

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

58,40

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground reference for digital logic

ÁÁÁÁÁ

VSS2

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

16,62

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground reference for digital I / O logic

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

FUNCTION

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of
the port D pins can be individually configured as a general-purpose I / O pin,
primary memory control signal (function A) or secondary memory control

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

primary memory control signal (function A), or secondary memory control
signal (function B). All chip selects are independent and can be used for
memory bank switching. Refer to Table 1 for function A memory accesses.

ÁÁÁÁÁ

ÁÁÁ

CSE2

ÁÁÁÁ

OCF

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select eighth output 2 goes low during memory accesses
I / O pin B: Opcode fetch goes low during the opcode fetch memory cycle.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

CSH3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 3 goes low during memory accesses.
I / O pin B: Reserved

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

CSH2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 2 goes low during memory accesses.
I / O pin B: Reserved

ÁÁÁÁÁ

ÁÁÁ

SYSCLK

ÁÁÁÁ

SYSCLK

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency.

ÁÁÁÁÁ

ÁÁÁ

R / W

ÁÁÁÁ

R / W

ÁÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A, B: Read / write output pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

CSPF

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select peripheral output for peripheral file goes low during
memory accesses.
I / O pin B: Reserved

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

CSH1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

EDS

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select half output 1 goes low during memory accesses.
I / O pin B: External data strobe output goes low during memory accesses from
external memory and has the same timings as the five chip selects.

ÁÁÁÁÁ

ÁÁÁ

CSE1

ÁÁÁÁ

WAIT

ÁÁÁ

ÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I / O pin A: Chip select eighth output goes low during memory accesses.
I / O pin B: Wait input pin extends bus signals.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SCITXD
SCIRXD
SCICLK

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

SCIIO1
SCIIO2
SCIIO3

ÁÁÁ

28
27
26

ÁÁÁ

30
29
28

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SCI transmit data output pin / general-purpose bidirectional pin (see Note 1)
SCI receive data input pin / general-purpose bidirectional pin
SCI bidirectional serial clock pin / general-purpose bidirectional pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

T1IC / CR
T1PWM
T1EVT

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

T1IO1
T1IO2
T1IO3

ÁÁÁ

44
43
41

ÁÁÁ

46
45
44

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer1 input capture / counter reset input pin / general-purpose bidirectional
pin
Timer1 pulse-width-modulation (PWM) output pin / general-purpose
bidirectional pin
Timer1 external event input pin / general-purpose bidirectional pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

T2AIC1 / CR
T2AIC2 / PWM
T2AEVT

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

T2AIO1
T2AIO2
T2AIO3

ÁÁÁ

25
24
23

ÁÁÁ

27
26
25

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Timer2A input capture 1 / counter reset input pin / general-purpose bidirectional
pin
Timer2A input capture 2 / PWM output pin / general-purpose bidirectional pin
Timer2A external event input pin / general-purpose bidirectional pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SPISOMI
SPISIMO
SPICLK

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

SPIIO1
SPIIO2
SPIIO3

ÁÁÁ

47
46
45

ÁÁÁ

49
48
47

ÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SPI slave output pin, master input pin / general-purpose bidirectional pin
SPI slave input pin, master output pin / general-purpose bidirectional pin
SPI bidirectional serial clock pin / general-purpose bidirectional pin

I = input, O = output
Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.
NOTE 1: The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A: Memory Accesses Locations for `x5x Devices

ÁÁÁÁÁÁÁÁÁ

FUNCTION A

ÁÁÁÁÁÁÁÁÁ

`X50, `X52, `X53, AND `X56

ÁÁÁÁÁÁÁÁÁ

`X58

ÁÁÁÁÁÁÁÁÁ

`X59

ÁÁÁÁÁÁÁÁÁ

CSEx

ÁÁÁÁÁÁÁÁÁ

2000h 3FFFh (8K bytes)

ÁÁÁÁÁÁÁÁÁ

A000h BFFFh (8K bytes)

ÁÁÁÁÁÁÁÁÁ

E000h EFFFh (4K bytes)

ÁÁÁÁÁÁÁÁÁ

CSHx

ÁÁÁÁÁÁÁÁÁ

8000h FFFFh (32K bytes)

ÁÁÁÁÁÁÁÁÁ

C000h FFFFh (16K bytes)

ÁÁÁÁÁÁÁÁÁ

F000h FFFFh (4K bytes)

ÁÁÁÁÁÁÁÁÁ

CSPF

ÁÁÁÁÁÁÁÁÁ

10C0h 10FFh (64 bytes)

ÁÁÁÁÁÁÁÁÁ

10C0h 10FFh (64 bytes)

ÁÁÁÁÁÁÁÁÁ

10C0h 10FFh (64 bytes)

TMS370Cx5x
8-BIT MICROCONTROLLER

SPNS010F DECEMBER 1986 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

functional block diagram

Program Memory

ROM: 4K, 8K, 12K, 16K,

32K, or 48K Bytes

EPROM: 16K, 32K, or

48K Bytes

VSS1

VCC1

RESET

XTAL2/
CLKIN

XTAL1

INT3

INT2

INT1

E0 E7

AN0 AN7

VCC2

VSS2

Data EEPROM

0, 256, or 512 Bytes

RAM

256, 512, 1K, 1.5K, or

3.5K Bytes

CPU

Port D

Port C

Port B

Watchdog

Timer 1

Timer 2A

Serial

Communications

Interface 1

Serial

Peripheral

Interface

Analog-to-Digital

Converter 1

System Control

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

T1PWM

T1EVT

T1IC / CR

T2AIC2 / PWM

T2AEVT

T2AIC1 / CR

SCICLK

SCITXD

SCIRXD

SPICLK

SPISIMO

SPISOMI

VSS3

VCC3

Port A

Interrupts

8/6

Memory Expansion

Data

Address LSbyte

Address MSbyte

Control

For the 64-pin devices, there are only six pins for port D.

description

The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control
through integration of advanced peripheral function modules and various on-chip memory configurations. The
TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families:
the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and
SE370C75x.

The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of
CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the
TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control,
computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory
configuration overview of the TMS370Cx5x devices.

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F DECEMBER 1986 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

description (continued)

Table 2. Memory Configurations

DEVICE

PROGRAM

MEMORY

(BYTES)

OFF-CHIP

MEMORY

EXP (BYTES)

DATA MEMORY

(BYTES)

OPERATING

MODES

PACKAGES

68 PIN PLCC/CLCC, OR

64 PIN PSDIP/CSDIP

ROM

EPROM

EXP. (BYTES)

RAM

EEPROM

64 PIN PSDIP/CSDIP

TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350

ÁÁÁÁÁÁÁÁ

TMS370C050A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C150A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C250A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

256

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C350A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452

ÁÁÁÁÁÁÁÁ

TMS370C052A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C352A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C452A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

256

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

TMS370Cx53: TMS370C353

ÁÁÁÁÁÁÁÁ

TMS370C353A

ÁÁÁ

12K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

1.5K

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756

ÁÁÁÁÁÁÁÁ

TMS370C056A

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C156A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C256A

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

56K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C356A

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C456A

ÁÁÁ

16K

ÁÁÁÁ

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C756A

ÁÁÁ

ÁÁÁÁ

16K

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758

ÁÁÁÁÁÁÁÁ

TMS370C058A

ÁÁÁ

32K

ÁÁÁÁ

ÁÁÁÁÁ

64K

ÁÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

TMS370C358A

ÁÁÁ

32K

ÁÁÁÁ

ÁÁÁÁÁ

64K

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C758A,
TMS370C758B

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

32K

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

64K

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC / NM PSDIP

TMS370Cx59: TMS370C059 AND TMS370C759

ÁÁÁÁÁÁÁÁ

TMS370C059A§

ÁÁÁ

48K

ÁÁÁÁ

ÁÁÁÁÁ

20K

ÁÁÁ

3.5K

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁÁ

TMS370C759A§

ÁÁÁ

ÁÁÁÁ

48K

ÁÁÁÁÁ

20K

ÁÁÁ

3.5K

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FN PLCC

EPROM DEVICE: SE370C756, SE370C758, and SE370C759

ÁÁÁÁÁÁÁÁ

SE370C756Aś

ÁÁÁ

ÁÁÁÁ

16K

ÁÁÁÁÁ

112K

ÁÁÁ

512

ÁÁÁÁ

512

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FZ CLCC / JN CSDIP

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

SE370C758Aś,
SE370C758Bś

ÁÁÁ

ÁÁÁÁ

ÁÁ

32K

ÁÁÁÁÁ

ÁÁÁ

64K

ÁÁÁ

ÁÁÁÁ

ÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

FZ CLCC / JN CSDIP

ÁÁÁÁÁÁÁÁ

SE370C759A§ś

ÁÁÁ

ÁÁÁÁ

48K

ÁÁÁÁÁ

20K

ÁÁÁ

3.5K

ÁÁÁÁ

256

ÁÁÁ

ÁÁÁÁÁÁÁÁ

FZ CLCC

C Microcomputer mode

P Microprocessor mode

TMS370C45x support ROM memory security. Refer to the program ROM section.
§ Only operate up to 3 MHz SYSCLK
ś System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

Part Number TMS370Cx5x