TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

CMOS / EEPROM/ EPROM Technologies on
a Single Device
Mask-ROM Devices for High-Volume

Production

 One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

 Reprogrammable-EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations
On-Chip Program Memory Versions

ROM: 8K Bytes
EPROM: 8K Bytes

Data EEPROM: 256 Bytes
Static RAM: 256 Bytes Usable as

Registers

Flexible Operating Features
Low-Power Modes: STANDBY and HALT
Commercial, Industrial, and Automotive

Temperature Ranges

 Clock Options

 Divide-by-1 (2 MHz 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

 Divide-by-4 (0.5 MHz 5 MHz SYSCLK)

 Supply Voltage (V

) 5 V

10%

Programmable Acquisition and Control
Timer (PACT) Module
Input Capture on up to Six Pins, Four of

Which Can Have a Programmable
Prescaler

 One Input Capture Pin Can Drive an 8-Bit

Event Counter

Up to Eight Timer-Driven Outputs
Interaction Between Event Counter and

Timer Activity

18 Independent Interrupt Vectors
Watchdog With Selectable Time-Out

Period

 Asynchronous Mini Serial

Communication Interface (Mini SCI)

Flexible Interrupt Handling
Two Software-Programmable Interrupt

Levels

Global- and Individual-Interrupt Masking
Programmable Rising- or Falling-Edge

Detect

 Individual-Interrupt Vectors

Eight-Channel 8-Bit Analog-to-Digital
Converter 1 (ADC1)

TMS370 Series Compatibility
Register-to-Register Architecture
256 General-Purpose Registers
14 Powerful Addressing Modes
Instructions Upwardly Compatible With

All TMS370 Devices

CMOS / TTL Compatible I / O Pins / Packages
All Peripheral Function Pins Software

Configurable for Digital I / O

14 Bidirectional Pins, Nine Input Pins
44-Pin Plastic and Ceramic Leaded Chip

Carrier (LCC) Packages

Workstation / PC-Based Development
System
C Compiler and C Source Debugger
Real-Time In-Circuit Emulation
Multi-Window User Interface
Microcontroller Programmer
Extensive breakpoint/Trace Capability

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OP2

MC
XTAL2/CLKIN
XTAL1
CP2
SCIRXD
CP6
AN7
AN6
AN5
AN4
V

SS3

18 19

INT1
INT2
INT3

CC1

CC3

A7
A6

SS1

A5
A4
A3

20 21 22 23

FZ AND FN PACKAGES

(TOP VIEW)

OP5

OP1

SCITXD

CP1

4 3

RESET

OP8

OP7

OP6

OP4

OP3

AN0

AN1

AN2

AN3

D7/CP5

D4/CP3

D6/CP4

42 41 40

24 25 26 27 28

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Pin Descriptions

ÁÁÁÁÁÁÁÁ

44 PINS

ÁÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ

NAME

ÁÁÁÁ

NO.

ÁÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

A0
A1
A2
A3
A4
A5
A6
A7

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

20
19
18
17
16
15
13
12

ÁÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A is a general-purpose bidirectional I / O port.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

D3
D4/CP3
D6/CP4
D7/CP5

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

23
22
24
21

ÁÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port D is a general-purpose bidirectional port.
Also configurable as SYSCLK (see Note 1)
PACT input capture 3 (see Note 2)
PACT input capture 4 (see Note 2)
PACT input capture 5 (see Note 2)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP1
CP2
CP6

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

40
36
34

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT Input capture pin 1
PACT Input capture pin 2
PACT Input capture pin 3

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AN0/E0
AN1/E1
AN2/E2
AN3/E3
AN4/E4
AN5/E5
AN6/E6
AN7/E7

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

25
26
27
28
30
31
32
33

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ADC1 analog input pins (AN0 AN7) / port E digital input pins (E0 E7)

Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog
input or positive reference input.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1
INT2
INT3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

7
8
9

ÁÁÁ

I/O
I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

External interrupt (non-maskable or maskable) / general-purpose input pin
External maskable interrupt input/general purpose bidirectional pin
External maskable interrupt input/general purpose bidirectional pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

OP1
OP2
OP3
OP4
OP5
OP6
OP7
OP8

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

42
43
44

1
2
3
4
5

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT output pin 1
PACT output pin 2
PACT output pin 3
PACT output pin 4
PACT output pin 5
PACT output pin 6
PACT output pin 7
PACT output pin 8

ÁÁÁÁÁ

SCIRXD
SCITXD

ÁÁÁÁ

35
41

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT mini SCI data receive input pin
PACT mini SCI data transmit output pin

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

RESET

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

I / O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,
RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP

ÁÁÁÁÁ

XTAL2 / CLKIN
XTAL1

ÁÁÁÁ

38
37

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal oscillator crystal input / External clock source input
Internal oscillator output for crystal

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

VCC1
VSS1
VCC3
VSS3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

10
14

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive supply voltage for digital logic and digital I/O pins
Ground reference for digital logic and digital I/O pins
ADC1 positive supply voltage and optional positive reference input
ADC1 ground supply and low reference input pin

I = input, O = output
NOTES:

1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers.
2. These digital I/O buffers are connected internally to some of the PACT module's input capture pins. This allows the microcontroller

to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave
the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

functional block diagram

Interrupts

CP1

SCITXD
SCIRXD

System
Control

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

Port A

Port D

PACT

Watchdog

INT1

E0-E7

AN0-AN7

XTAL1

XTAL2/

CLKIN

RESET

SS1

VCC1

Program Memory

ROM: 8K Bytes

EPROM: 8K Bytes

ĎĎĎĎĎ

Data EEPROM

256 Bytes

A-to-D

Converter 1

VCC3

VSS3

Mini SCI

CPU

RAM

Register File

256 Bytes

CP6

OP1

OP8

.
.

INT2

INT3

description

The TMS370C032A, TMS370C332A, TMS370C732A, and SE370C732A devices are members of the TMS370
family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx32 refers to these
devices. The TMS370 family provides cost-effective real-time system control through integration of advanced
peripheral-function modules and various on-chip memory configurations.

The TMS370Cx32 family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of
CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx32 devices attractive for system designs for automotive electronics, industrial motors, computer
peripheral controls, telecommunications, and consumer applications.

All TMS370Cx32 devices contain the following on-chip peripheral modules:

Programmable acquisition and control timer (PACT)

Asynchronous mini SCI

PACT watchdog timer

Eight channel, 8-bit analog-to-digital converter 1 (ADC1)

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx32 devices.

Table 1. Memory Configurations

ÁÁÁÁÁÁÁ

DEVICE

ÁÁÁÁÁÁÁÁÁÁ

PROGRAM MEMORY

(BYTES)

ÁÁÁÁÁÁÁÁÁ

DATA MEMORY

(BYTES)

ÁÁÁÁÁÁÁÁÁÁÁ

44 PIN PACKAGES

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ROM

ÁÁÁÁÁ

EPROM

ÁÁÁÁÁ

RAM

ÁÁÁÁÁ

EEPROM

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

TMS370C032A

ÁÁÁÁÁÁ

ÁÁÁÁÁ

256

ÁÁÁÁÁ

256

ÁÁÁÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁ

TMS370C332A

ÁÁÁÁÁÁ

ÁÁÁÁÁ

256

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁ

TMS370C732A

ÁÁÁÁÁÁ

ÁÁÁÁÁ

256

ÁÁÁÁÁ

256

ÁÁÁÁÁÁÁÁÁÁÁ

FN PLCC

ÁÁÁÁÁÁÁ

SE370C732A

ÁÁÁÁÁÁ

ÁÁÁÁÁ

256

ÁÁÁÁÁ

256

ÁÁÁÁÁÁÁÁÁÁÁ

FZ CLCC

System evaluators and development are for use only in prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of Table 1 indicates the
configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2. ROM
devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE

CLOCK

LOW-POWER MODE

EPROM A

Divide-by-4 (Standard oscillator)

Enabled

ROM A

Divide by 4 or Divide by 1 (PLL)

Enabled or disabled

ROM A

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Refer to the "device numbering conventions" section for device nomenclature and to the "device part numbers" section for ordering.

The 8K bytes of mask-programmable ROM in the associated TMS370Cx32 devices are replaced in the
TMS370C732A with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical
except for the TMS370C332A which does not have EEPROM memory. The OTP (TMS370C732A) and
reprogrammable (SE370C732A) devices are available.

The TMS370C732A OTP device is available in a plastic package. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx32 family or for low-volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C732A has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development / prototyping phase of design. The SE370C732A device allows quick updates to
breadboards and prototype systems while iterating initial designs.

The TMS370Cx32 family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In
the STANDBY mode, the internal oscillator, the PACT counter, and PACT's first command / definition entry
remain active. This allows the PACT module to bring the device out of STANDBY mode. In the HALT mode, all
device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.

The TMS370Cx32 features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx32 family is fully
instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller
family.

The TMS370Cx32 has a PACT module that acts as a timer coprocessor by gathering timing information on input
signals and controlling output signals with little or no intervention by the CPU. The coprocessor nature of this
module allows for levels of flexibility and power not found in traditional microcontroller timers.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

description (continued)

The TMS370Cx32 family provides the system designer with an economical, efficient solution to real-time control
applications. The PACT compact development tool (CDT

) solves the challenge of efficiently developing the

software and hardware required to design the TMS370Cx32 into an ever-increasing number of complex
applications. The application source code can be written in assembly and C language, and the output code can
be generated by the linker. Precise real-time, in-circuit emulation and extensive symbolic debug and analysis
tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle.

The TMS370Cx32 family together with the TMS370 PACT CDT370, BP programmer, starter kit, software tools,
the SE370C732A reprogrammable devices, comprehensive product documentation, and customer support
provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU on the TMS370Cx32 device is the high-performance 8-bit TMS370 CPU module. The 'x32 implements
an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The
complete 'x32 instruction map is shown in Table 15.

The '370Cx32 CPU architecture provides the following components:

CPU registers:

A stack pointer (SP) that points to the last entry in the memory stack

A status register (ST) that monitors the operation of the instructions and contains the global interrupt-enable
bits

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions, general
purpose register, dual-port RAM, or the stack

The upper 128-bytes of the register file is called dual-port RAM that contains the capture registers, the
circular buffer, and a command/definition area.

A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and
EEPROM/ EPROM programming control

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off
conditions

8K-byte ROM or 8K-byte EPROM

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

central processing unit (CPU) (continued)

Figure 1 Illustrates the CPU registers and memory blocks.

Reserved

Peripheral File

01FFh

0200h

1000h
10BFh
10C0h
1EFFh

1F00h

5FFFh
6000h

Interrupts and Reset Vectors;

Trap Vectors

0FFFh

Reserved

7FFFh

RAM (Includes up to 256-Byte Registers File)

Program Counter

Legend:

Z=Zero

IE1 = Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2 = Level 2 interrupts Enable

IE1

IE2

Status Register (ST)

Stack Pointer (SP)

R0(A)

R1(B)

R127

0000h

0001h

0002h

007Fh

R255

0003h

00FFh

1FFFh

2000h

7F9Ch

7F9Bh

256-Byte RAM

00FFh

0100h
017Fh

0180h

128-Byte PACT Dual-Port RAM

0000h

Reserved

256-Byte Data EEPROM

Reserved

8K-Byte ROM/EPROM

Reserved

FFFFh

8000h

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer's Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read / write memory. Typically, the stack
is used to store the return address on subroutine calls as well as the ST contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits.

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional-jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

central processing unit (CPU) (continued)

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁ

IE2

ÁÁÁÁ

IE1

Reserved

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

RW-0

ÁÁÁÁÁ

RW-0

ÁÁÁÁ

RW-0

ÁÁÁÁÁÁ

ÁÁÁÁÁ

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the
PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the
contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the
contents of the reset vector.

Memory

Program Counter (PC)

PCH

PCL

0000h

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx32 architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input / output is memory mapped in this same common
address space. As shown in Figure 3, the TMS370Cx32 provides memory-mapped RAM, ROM, EPROM, data
EEPROM, I / O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I / O port control, peripheral status and control, EEPROM, EPROM, and
system-wide control functions. The peripheral file is located between 1000h to 107Fh and is divided logically
into eight peripheral file frames of 16 bytes each. The eight PF frames consist of five control frames and three
reserved frames.Each on-chip peripheral is assigned to a separate frame through which peripheral control and
data information is passed.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

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central processing unit (CPU) (continued)

256-Byte RAM (0000h00FFh)

Peripheral File

Reserved

7FC0h 7FDFh

PACT Interrupt 1-18

7FEEh 7FF7h

Reserved

7FECh 7FEDh

Interrupt 1

Reset

1020h 102Fh

Digital Port Control

Vectors

ADC1

7FFCh 7FFDh

7FFEh 7FFFh

0000h

0100h

0080h

0FFFh

1000h

10BFh

10C0h

1EFFh

1F00h

1FFFh

2000h

5FFFh

6000h

FFFFh

00FFh

Interrupts and Reset Vectors;

Trap and PACT Vectors

7F9Bh
7F9Ch

7FFFh

8000h

7FF8h 7FF9h

7FFAh 7FFBh

Peripheral File Control Registers

1010h 101Fh

1050h 105Fh

System Control

1030h 103Fh

1040h 104Fh

ADC1 Peripheral Control

Trap 15 0

Reserved

256-Byte Data EEPROM

Reserved

8K-Byte ROM/EPROM

Reserved

7F9Ch 7FBFh

7FE0h 7FEBh

1000h 100Fh

1060h 106Fh

1070h 107Fh

Reserved

PACT Peripheral Control

Reserved

Interrupt 2

Interrupt 3

DualPort RAM (0080h00FFh)

Reserved means that the address space is reserved for future expansion.

Figure 3. TMS370Cx32 Memory Map

RAM / register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read / write memory, program
memory, or the stack instructions. The TMS370Cx32 devices contain 256 bytes of internal RAM,
memory-mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is
shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

dual-port RAM

The upper 128 bytes of the register files (0080h 00FFh) can be used by the PACT module to contain
commands and definitions as well as timer values. Any RAM not used by PACT can be used as additional CPU
register or as general-purpose memory.

TMS370Cx32

8-BIT MICROCONTROLLER

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peripheral file (PF)

The TMS370Cx32 control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
shows the TMS370Cx32 PF address map.

Table 4. TMS370Cx32 Peripheral File Address Map

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ADDRESS RANGE

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

PERIPHERAL FILE

DESIGNATOR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁÁÁ

1000h 100Fh

ÁÁÁÁÁÁÁ

P000 P00F

Reserved

ÁÁÁÁÁÁÁ

1010h 101Fh

ÁÁÁÁÁÁÁ

P010 P01F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System and EPROM / EEPROM control registers

ÁÁÁÁÁÁÁ

1020h 102Fh

ÁÁÁÁÁÁÁ

P020 P02F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Digital I / O port control registers

ÁÁÁÁÁÁÁ

1030h 103Fh

ÁÁÁÁÁÁÁ

P030 P03F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1040h 104Fh

ÁÁÁÁÁÁÁ

P040 P04F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT registers

ÁÁÁÁÁÁÁ

1050h 106Fh

ÁÁÁÁÁÁÁ

P050 P06F

Reserved

ÁÁÁÁÁÁÁ

1070h 107Fh

ÁÁÁÁÁÁÁ

P070 P07F

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Analog-to-digital converter 1 registers

ÁÁÁÁÁÁÁ

1080h 10FFh

ÁÁÁÁÁÁÁ

P080 P0FF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

data EEPROM

The TMS370Cx32 devices, containing 256 bytes of data EEPROM, have a memory that is mapped beginning
at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled
by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming
algorithm examples are available in the

TMS370 Family User's Guide (literature number SPNU127) or the

TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:

Programming:

Bit-, byte-, and block-write / erase modes

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame
beginning at location P01A. See Table 5.

In-circuit programming capability. There is no need to remove the device to program it.

Write protection. Writes to the data EEPROM are disabled during the following conditions.

Reset. All programming of the data EEPROM module is halted.

Write protection active. There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ÁÁÁÁÁ

ADDRESS

ÁÁÁÁÁ

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

NAME

ÁÁÁÁÁ

P01A

ÁÁÁÁÁ

DEECTL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data EEPROM Control Register

ÁÁÁÁÁ

P01B

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

P01C

ÁÁÁÁÁ

EPCTLL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Program EPROM Control Register Low Array

TMS370Cx32
8-BIT MICROCONTROLLER

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program EPROM

The TMS370C732 device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing
through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading
other internal memory. During programming, the EPROM is controlled by the EPROM control register
(EPCTLL). The program EPROM module features include:

Programming

In-circuit programming capability if V

is applied to MC

Control register: EPROM programming is controlled by the EPROM control register (EPCTLL) located
in the peripheral file (PF) frame at location P01C as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions:

Reset: All programming to the EPROM module is halted

Low-power modes

13 V not applied to MC

program ROM

The program ROM consists of 8K bytes of mask programmable read-only memory. The program ROM is used
for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device
fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx32 CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

PACT watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD
key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370

Family User's Guide (literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the

TMS370 Family User's Guide (literature number SPNU127) for more information.

External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 Family User's Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the 'x32 device to reset external system components. Additionally, if a cold start condition
(V

is off for several hundred milliseconds) or oscillator failure occurs or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4) and the cold-start flag
(COLD START, SCCR0.7) to determine the source of the reset. A reset does not clear these flags. Table 6
depicts the reset sources. If none of the sources indicated in Table 1 caused the reset, then the RESET pin was
pulled low by the external hardware or the PACT module's watchdog.

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and 7FECh through 7FFFh are reserved for interrupt and reset

vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. PACT interrupts are
located between addresses 7F9Ch and 7FBFh.

TMS370Cx32

8-BIT MICROCONTROLLER

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system reset (continued)

Table 6. Reset Sources

ÁÁÁÁÁ

REGISTER

ÁÁÁÁÁÁ

ADDRESS

ÁÁÁÁ

ÁÁÁÁÁ

BIT NO.

ÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁÁÁÁÁÁÁ

SOURCE OF RESET

ÁÁÁÁÁ

SCCR0

ÁÁÁÁÁÁ

1010h

ÁÁÁÁ

P010

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

COLD START

ÁÁÁÁÁÁÁÁÁÁ

Cold (power-up)

ÁÁÁÁÁ

SCCR0

ÁÁÁÁÁÁ

1010h

ÁÁÁÁ

P010

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

OSC FLT FLAG

ÁÁÁÁÁÁÁÁÁÁ

Oscillator out of range

Once a reset is activated, the following sequence of events occurs:

The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

Registers A and B are initialized to 00h (no other RAM is changed).

The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

Program execution begins with an opcode fetch from the address pointed to the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.

TMS370Cx32
8-BIT MICROCONTROLLER

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of
the ST.

GROUP 2

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT

Level 2 INT

PACT 3 PRI

Priority

Cmd/Def Entry 7

Cmd/Def Entry 6

Cmd/Def Entry 5

Cmd/Def Entry 4

Cmd/Def Entry 3

Cmd/Def Entry 2

AD INT

AD PRI

ADC1

STATUS REG

EXT INT1

INT1 PRI

INT1

Cmd/Def Entry 1

Cmd/Def Entry 0

GROUP 3

PACT 1 PRI

Overflow

CP1 Edge

CP2 Edge

CP3 Edge

CP4 Edge

CP5 Edge

CP6 Edge

Circular Buffer

GROUP 1

PACT 2 PRI

SCI TXINT

SCI RXINT

PACT

Default Timer

EXT INT3

INT3

EXT INT2

INT2

INT3 PRI

INT2 PRI

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is selectively configured on either the high- or
low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

TMS370Cx32

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.

The TMS370Cx32 has 22 hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt
has a dedicated vector located in program memory through which control is passed to the interrupt service
routines. A system interrupt may have multiple interrupt sources. All the interrupt sources are individually
maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit
is individually readable for software polling or for determining which interrupt source generated the associated
system interrupt.

Nineteen of the system interrupts are generated by on-chip peripheral functions, and three external interrupts
are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input
polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as
either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked
by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software configured as general-purpose input/output pins if the
interrupt function is not required (INT1 can be similarly configured as an input pin).

TMS370Cx32
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interrupts (continued)

Table 7. Hardware System Interrupts

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

INTERRUPT

SOURCE

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

INTERRUPT

FLAG

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

OSC FLT FLG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SYSTEM

INTERRUPT

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

VECTOR

ADDRESS

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MODULE

PRIORITY

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PRIORITY

GROUP

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

RESET

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

External RESET
Watchdog Overflow
Oscillator Fault

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

COLD START
(No Flag)
OSC FLT FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

RESET

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

7FFEh, 7FFFh

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

INT1

ÁÁÁÁÁÁÁÁÁ

External Interrupt 1

ÁÁÁÁÁÁ

INT1 FLAG

ÁÁÁÁÁ

INT1

ÁÁÁÁÁÁ

7FFCh, 7FFDh

ÁÁÁÁ

ÁÁÁÁÁÁ

INT2

ÁÁÁÁÁÁÁÁÁ

External Interrupt 2

ÁÁÁÁÁÁ

INT2 FLAG

ÁÁÁÁÁ

INT2

ÁÁÁÁÁÁ

7FFAh, 7FFBh

ÁÁÁÁ

ÁÁÁÁÁÁ

INT3

ÁÁÁÁÁÁÁÁÁ

External Interrupt 3

ÁÁÁÁÁÁ

INT3 FLAG

ÁÁÁÁÁ

INT3

ÁÁÁÁÁÁ

7FF8h, 7FF9h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Circular Buffer

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

Buffer Half/Full
Interrupt Flag

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

BUFINT

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

7FB0h, 7FB1h

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT CP6 Event

ÁÁÁÁÁÁ

CP6 INT FLAG

ÁÁÁÁÁ

CP6INT

ÁÁÁÁÁÁ

7FB2h, 7FB3h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT CP5 Event

ÁÁÁÁÁÁ

CP5 INT FLAG

ÁÁÁÁÁ

CP5INT

ÁÁÁÁÁÁ

7FB4h, 7FB5h

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 1)

ÁÁÁÁÁÁÁÁÁ

PACT CP4 Event

ÁÁÁÁÁÁ

CP4 INT FLAG

ÁÁÁÁÁ

CP4INT

ÁÁÁÁÁÁ

7FB6h, 7FB7h

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 1)

ÁÁÁÁÁÁÁÁÁ

PACT CP3 Event

ÁÁÁÁÁÁ

CP3 INT FLAG

ÁÁÁÁÁ

CP3INT

ÁÁÁÁÁÁ

7FB8h, 7FB9h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT CP2 Event

ÁÁÁÁÁÁ

CP2 INT FLAG

ÁÁÁÁÁ

CP2INT

ÁÁÁÁÁÁ

7FBAh, 7FBBh

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT CP1 Event

ÁÁÁÁÁÁ

CP1 INT FLAG

ÁÁÁÁÁ

CP1INT

ÁÁÁÁÁÁ

7FBCh, 7FBDh

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Default Timer
Overflow

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

DEFTIM OVRFL INT
FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

POVRL

INT

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

7FBEh, 7FBFh

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 2)

ÁÁÁÁÁÁÁÁÁ

PACT SCI Rx Int

ÁÁÁÁÁÁ

PACT RX RDY

ÁÁÁÁÁ

PRXINT

ÁÁÁÁÁÁ

7F9Eh, 7F9Fh

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 2)

ÁÁÁÁÁÁÁÁÁ

PACT SCI Tx Int

ÁÁÁÁÁÁ

PACT TX RDY

ÁÁÁÁÁ

PTXINT

ÁÁÁÁÁÁ

7F9Ch, 7F9Dh

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 0

ÁÁÁÁÁÁ

CMD/DEF INT 0 FLAG

ÁÁÁÁÁ

CDINT 0

ÁÁÁÁÁÁ

7FA0h, 7FA1h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 1

ÁÁÁÁÁÁ

CMD/DEF INT 1 FLAG

ÁÁÁÁÁ

CDINT 1

ÁÁÁÁÁÁ

7FA2h, 7FA3h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 2

ÁÁÁÁÁÁ

CMD/DEF INT 2 FLAG

ÁÁÁÁÁ

CDINT 2

ÁÁÁÁÁÁ

7FA4h, 7FA5h

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 3)

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 3

ÁÁÁÁÁÁ

CMD/DEF INT 3 FLAG

ÁÁÁÁÁ

CDINT 3

ÁÁÁÁÁÁ

7FA6h, 7FA7h

ÁÁÁÁ

ÁÁÁÁÁÁ

PACT (Group 3)

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 4

ÁÁÁÁÁÁ

CMD/DEF INT 4 FLAG

ÁÁÁÁÁ

CDINT 4

ÁÁÁÁÁÁ

7FA8h, 7FA9h

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 5

ÁÁÁÁÁÁ

CMD/DEF INT 5 FLAG

ÁÁÁÁÁ

CDINT 5

ÁÁÁÁÁÁ

7FAAh, 7FABh

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 6

ÁÁÁÁÁÁ

CMD/DEF INT 6 FLAG

ÁÁÁÁÁ

CDINT 6

ÁÁÁÁÁÁ

7FACh, 7FADh

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

PACT Cmd/Def Entry 7

ÁÁÁÁÁÁ

CMD/DEF INT 7 FLAG

ÁÁÁÁÁ

CDINT 7

ÁÁÁÁÁÁ

7FAEh, 7FAFh

ÁÁÁÁ

ÁÁÁÁÁÁ

ADC1

ÁÁÁÁÁÁÁÁÁ

ADC1 Conversion Complete

ÁÁÁÁÁÁ

AD INT FLAG

ÁÁÁÁÁ

ADINT

ÁÁÁÁÁÁ

7FECh, 7FEDh

ÁÁÁÁ

Relative priority within an interrupt level
Release microcontroller from STANDBY and HALT low-power modes

privileged operation and EEPROM write protection override

The TMS370Cx32 family is designed with significant flexibility to enable the designer to software-configure the
system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of
operation ensures the integrity of the system configuration, once it is defined for an application. Following a
hardware reset, the TMS370Cx32 operates in the privileged mode, where all peripheral file registers have
unrestricted read / write access, and the application program configures the system during the initialization
sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is
set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within
the PF. Table 8 displays the system-configuration bits which are write-protected during the nonprivileged mode
and must be configured by software prior to exiting the privileged mode.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

privileged operation and EEPROM write protection override (continued)

Table 8. Privilege Bits

ÁÁÁÁÁÁÁÁÁ

REGISTER

ÁÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁÁ

NAME

ÁÁÁÁÁ

LOCATION

ÁÁÁÁÁÁÁÁÁÁ

CONTROL BIT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SCCRO

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P010.5
P010.6

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

PF AUTO WAIT
OSC POWER

ÁÁÁÁÁ

SCCR1

ÁÁÁÁÁ

P011.2
P011.4

ÁÁÁÁÁÁÁÁÁÁ

MEMORY DISABLE
AUTOWAIT DISABLE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SCCR2

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P012.0
P012.1
P012.3
P012.4
P012.6
P012.7

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN / IDLE
HALT / STANDBY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACTSCR

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P040.0
P040.1
P040.2
P040.3
P040.4

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

PACT PRESCALE SELECT 0
PACT PRESCALE SELECT 1
PACT PRESCALE SELECT 2
PACT PRESCALE SELECT 3
FAST MODE SELECT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACTPRI

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P04F.0
P04F.1
P04F.2
P04F.3
P04F.4
P04F.5
P04F.7

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

PACT WD PRESCALE SELECT 0
PACT WD PRESCALE SELECT 1
PACT MODE SELECT
PACT GROUP 3 PRIORITY
PACT GROUP 2 PRIORITY
PACT GROUP 1 PRIORITY
PACT STEST

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ADPRI

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P07F.5
P07F.6
P07F.7

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

AD ESPEN
AD PRIORITY
AD STEST

The privilege bits are shown in a bold typeface in the peripheral file

frame 1 section.

low-power and IDLE modes

The TMS370Cx32 devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The
HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, the PACT counter, and the first PACT command entry remain active in
all modules. System processing is suspended until a qualified interrupt (hardware RESET or external interrupt
on INT1, INT2, or INT3) is detected.

In the HALT mode (HALT / STANDBY = 1), the TMS370Cx32 is placed in its lowest power consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET or external interrupt on the INT1, INT2, or INT3) is
detected. The power-down mode-selection bits are summarized in Table 9.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

low-power and IDLE modes (continued)

Table 9. Low-Power / Idle Control Bits

ÁÁÁÁÁÁÁÁÁÁÁÁ

POWER-DOWN CONTROL BITS

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PWRDWN / IDLE

(SCCR2.6)

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

HALT / STANDBY

(SCCR2.7)

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

MODE SELECTED

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

STANDBY

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

HALT

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

IDLE

X = don't care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.

To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (SP, PC, and ST), I / O pin direction and output data, and status registers of all on-chip peripheral
functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking
of the WD timer is inhibited.

clock modules

The 'x32 family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The 'x32 masked-ROM devices offer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The '732A
EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.

The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system
clock (SYSCLK) frequency, whereas the divide-by-4 produces a SYSCLK which is one-fourth the frequency of
the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by
four, and the clock module then divides the resulting signal by four to provide the four-phased internal system
clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows:

Divide-by-4 option : SYSCLK

external resonator frequency

CLKIN

Divide-by-1 option : SYSCLK

external resonator frequency

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the reduced EMI. The harmonics of low-speed
resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper
decay of emissions produced by the oscillator.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

system configuration registers

Table 10, contains system-configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface and shaded areas.

Table 10. Peripheral File Frame 1: System-Configuration Registers

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁ

REG

ÁÁÁ

P010

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

OSC FLT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MC PIN

WPO

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MC PIN

DATA

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P /

MODE

ÁÁÁ

SCCR0

ÁÁÁ

P011

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AUTO

WAIT

DISABLE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MEMORY

DISABLE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

SCCR1

ÁÁÁ

P012

HALT /

STANDBY

PWRDWN /

IDLE

BUS

STEST

CPU

STEST

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT1

NMI

PRIVILEGE

DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

P013

P016

Reserved

ÁÁÁ

P017

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT1

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1

PIN DATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT1

POLARITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1

PRIORITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1

ENABLE

ÁÁÁ

INT1

ÁÁÁ

P018

ÁÁÁÁ

INT2

FLAG

ÁÁÁÁÁ

INT2

PIN DATA

ÁÁÁÁ

ÁÁÁÁÁ

INT2

DATA DIR

ÁÁÁÁ

INT2

DATA OUT

ÁÁÁÁ

INT2

POLARITY

ÁÁÁÁÁ

INT2

PRIORITY

ÁÁÁÁÁ

INT2

ENABLE

ÁÁÁ

INT2

ÁÁÁ

P019

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT3

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT3

PIN DATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT3

DATA DIR

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT3

DATA OUT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT3

POLARITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT3

PRIORITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT3

ENABLE

ÁÁÁ

INT3

ÁÁÁ

P01A

ÁÁÁÁ

BUSY

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

W1W0

ÁÁÁÁÁ

EXE

ÁÁÁ

DEECTL

ÁÁÁ

P01B

Reserved

ÁÁÁ

P01C

ÁÁÁÁ

BUSY

ÁÁÁÁÁ

VPPS

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

EXE

ÁÁÁ

EPCTLL

ÁÁÁ

P01D

P01E

P01F

Reserved

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 shows the specific
addresses, registers, and control bits within this peripheral file frame. Table 12 shows the port configuration
register setup.

Table 11. Peripheral File Frame 2: Digital Port-Control Registers

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁ

BIT 6

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

P020

Reserved

ÁÁÁÁ

APORT1

ÁÁÁÁ

P021

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Control Register 2 (must be 0)

ÁÁÁÁ

APORT2

ÁÁÁÁ

P022

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Data

ÁÁÁÁ

ADATA

ÁÁÁÁ

P023

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Direction

ÁÁÁÁ

ADIR

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P024

P02B

Reserved

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P02C

ÁÁÁÁÁÁÁ

Port D Control Register 1

(must be 0)

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Control Register 1

(must be 0)

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

DPORT1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P02D

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Port D Control Register 2

(must be 0)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Control Register 2

(must be 0)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

DPORT2

ÁÁÁÁ

P02E

ÁÁÁÁÁÁÁ

Port D Data

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Data

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

DDATA

ÁÁÁÁ

P02F

ÁÁÁÁÁÁÁ

Port D Direction

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Direction

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

DDIR

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 12. Port Configuration Register Setup

ÁÁÁÁÁÁÁÁÁÁ

PORT

ÁÁÁÁÁÁÁÁÁ

PIN

ÁÁÁÁÁÁÁÁÁ

abcd
00q1

ÁÁÁÁÁÁÁÁÁ

abcd
00y0

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

0 7

ÁÁÁÁÁÁÁÁÁ

Data out q

ÁÁÁÁÁÁÁÁÁ

Data In y

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

3, 4, 6, 7

ÁÁÁÁÁÁÁÁÁ

Data out q

ÁÁÁÁÁÁÁÁÁ

Data In y

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

a = Port x Control Register 1
b = Port x Control Register 2

c = Data

d = Direction

programmable acquisition and control timer (PACT) module

Traditionally, timers in microcontrollers provide limited capture and compare functions consuming significant
CPU processing power, leading to inaccurate timings due to interrupt latencies. The programmable acquisition
and control timer (PACT8) acts as a coprocessor combining configurable capture and compare features, within
a flexible dual-port RAM, able to run real-time tasks with little or no CPU intervention. The PACT structure allows
concatenation of tasks, thus enabling the CPU to perform data manipulation while the PACT module both
captures and outputs real-time-related information. Since all the PACT control information is held within the
dual-port RAM, the CPU can access these parameters quickly.

To use the PACT, the user must set up three distinct areas of memory. The first is the dual-port RAM, which
contains the capture area, the commands, and the timer definitions. The second is the peripheral frame. The
third is an area near the end of the program memory which holds the interrupt vectors of PACT.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

programmable acquisition and control timer (PACT) module (continued)

The PACT module features include the following:

Input-capture functions on up to six input pins (CP1 to CP6), depending on the mode selected:

Mode A: CP12 are dedicated capture, CP36 are circular-buffer capture, and CP6 is an event pin.

Mode B: CP14 are dedicated capture, CP56 are circular-buffer capture, and CP6 is an event pin.

Multiple timer-driven outputs on eight pins (OP1 to OP8)

Standard compare command: sets or clears an output pin whenever the timer/counter is equal to a
certain value

Virtual timers: Enable variations of the PWM's period and provides periodic interrupts to the processor.

Double event-compare command: Comparisons of the 8-bit event counter with two event-compare
values and the actions that can be performed are based on each value.

Event-compare 1 matching the event counter: sets or resets the selected output pin (OP1OP8),
generates interrupt, and generates a 32-bit capture into the circular buffer.

Event-compare 2 matching the event counter: sets or resets the selected output pin (OP1OP8),
generates interrupt, generates a 32-bit capture into the circular buffer, and resets the 20-bit default
timer.

Offset timer definition-time from last event:

Generates an interrupt when the maximum event count is reached

Stores the 16-bit virtual timer in the circular buffer on each event

Stores the 20-bit default timer and 8-bit event counter in the circular buffer when the maximum
event count is reached

Resets the 20-bit hardware default timer when the maximum event count is reached

Conditional-compare command has a timer-compare value and an event-compare value.

Generates an interrupt when the event-compare value equals the event counter and the
timer-compare value equals the last defined timer

Sets or clears one of the seven output pins (OP1OP7) when the event compare value equals the
event counter and the timer-compare value equals the last defined timer

Baud rate timer definition: runs the mini-serial communications port built into the PACT module.

Configurable timer overflow rates

One 8-bit event counter driven by CP6

Up to 20-bit timer capability

Interaction between event counter and timer activity

18 independent interrupt vectors with two priority levels

Integrated, configurable watchdog with selectable time-out period

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

PACT control registers

The PACT module is controlled and accessed through registers in peripheral frame 4. These registers are listed
in Table 13. The bits in shaded boxes are privileged mode bits; that is, they can be written to only in the privileged
mode.

Table 13. PACT Control Registers

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

BIT 1

ÁÁÁÁ

BIT 0

ÁÁÁÁ

REG

ÁÁÁ

P040

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

DEFTIM

OVRFL

INT ENA

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

DEFTIM

OVRFL

INT FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA ENA

FAST

MODE

SELECT

PACT

PRESCALE

SELECT3

PACT

PRESCALE

SELECT2

PACT

PRESCALE

SELECT1

PACT

PRESCALE

SELECT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACTSCR

ÁÁÁ

P041

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

INT ENA

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT 5

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CMD/DEF

AREA

START BIT 4

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT 3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT 2

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CDSTART

ÁÁÁ

P042

CMD/DEF

AREA

END BIT 6

CMD/DEF

AREA

END BIT 5

CMD/DEF

AREA

END BIT 4

CMD/DEF

AREA

END BIT 3

CMD/DEF

AREA END

BIT 2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CDEND

ÁÁÁ

P043

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 5

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

BUFFER

POINTER

BIT 4

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 2

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

BUFFER

POINTER

BIT 1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFPTR

ÁÁÁ

P044

Reserved

ÁÁÁÁ

ÁÁÁ

P045

ÁÁÁÁ

PACT

RXRDY

ÁÁÁÁÁ

PACT

TXRDY

ÁÁÁÁ

PACT

PARITY

ÁÁÁÁÁ

PACT FE

ÁÁÁÁ

PACT SCI

RX INT ENA

ÁÁÁÁ

PACT SCI

TX INT ENA

ÁÁÁÁÁ

ÁÁÁÁ

PACT SCI

SW RESET

ÁÁÁÁ

SCICTLP

ÁÁÁ

P046

PACT

RXDT7

PACT

RXDT6

PACT

RXDT5

PACT

RXDT4

PACT

RXDT3

PACT

RXDT2

PACT

RXDT1

PACT

RXDT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

RXBUFP

ÁÁÁ

P047

ÁÁÁÁ

PACT

TXDT7

ÁÁÁÁÁ

PACT

TXDT6

ÁÁÁÁ

PACT

TXDT5

ÁÁÁÁÁ

PACT

TXDT4

ÁÁÁÁ

PACT

TXDT3

ÁÁÁÁ

PACT

TXDT2

ÁÁÁÁÁ

PACT

TXDT1

ÁÁÁÁ

PACT

TXDT0

ÁÁÁÁ

TXBUFP

ÁÁÁ

P048

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP8

STATE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT OP7

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP6

STATE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT OP5

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP4

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP3

STATE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT OP2

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP1

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PSTATE

ÁÁÁ

P049

CMD/DEF

INT 7 FLAG

CMD/DEF

INT 6 FLAG

ÁÁÁÁ

CMD/DEF

INT 5 FLAG

ÁÁÁÁÁ

CMD/DEF

INT 4 FLAG

ÁÁÁÁ

CMD/DEF

INT 3 FLAG

ÁÁÁÁ

CMD/DEF

INT 2 FLAG

ÁÁÁÁÁ

CMD/DEF

INT 1 FLAG

ÁÁÁÁ

CMD/DEF

INT 0 FLAG

ÁÁÁÁ

CDFLAGS

ÁÁÁ

P04A

CP2 INT

ENA

CP2 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP2 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP2 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 INT

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP1 CAPT

RISING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL1

ÁÁÁ

P04B

CP4 INT

ENA

CP4 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP4 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP4 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 INT

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP3 CAPT

RISING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL2

ÁÁÁ

P04C

CP6 INT

ENA

CP6 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP6 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP6 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 INT

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP5 CAPT

RISING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL3

ÁÁÁ

P04D

BUFFER

HALF/FULL

INT ENA

BUFFER

HALF/FULL

INT FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 3

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP6 EVENT

ONLY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

EVENT

COUNTER

SW RESET

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

OP/ SET/CLR

SELECT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPPRE

ÁÁÁ

P04E

WATCHDOG RESET KEY

ÁÁÁÁ

WDRST

ÁÁÁ

P04F

PACT

STEST

PACT

SUSPEND

PACT

GROUP 1

PRIORITY

PACT

GROUP 2

PRIORITY

PACT

GROUP 3

PRIORITY

PACT

MODE

SELECT

PACT WD

PRESCALE

SELECT 1

PACT WD

PRESCALE

SELECT 0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACTPRI

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

analog-to-digital converter 1 module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal
sample-and-hold circuitry. The module has four multiplexed analog input channels that allow the processor to
convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

Minimum conversion time: 32.8

s at 5 MHz SYSCLK

Ten external pins:

Eight analog-input channels (AN0 AN7), any of which can be software-configured as digital inputs
(E0 E7) when not needed as analog channels

AN1 AN7 also can be configured as positive-input voltage reference.

CC3

: ADC1 module high-voltage reference input

SS3

: ADC1 module low-voltage reference input

The ADDATA register, which contains the digital result of the last ADC1 conversion.

ADC1 operations can be accomplished through either interrupt-driven or polled algorithms.

Six ADC1 module control registers located in the control-register frame beginning at address 1070h

The ADC1 module control registers are listed in Table 14.

Table 14. ADC1 Module Control Register Memory Map

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁ

BIT 6

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

BIT 1

ÁÁÁÁ

BIT 0

ÁÁÁÁ

REG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P070

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CONVERT

START

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

SAMPLE

START

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

REF VOLT

SELECT2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

REF VOLT

SELECT1

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

REF VOLT

SELECT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD INPUT

SELECT2

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AD INPUT

SELECT1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD INPUT

SELECT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ADCTL

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P071

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD READY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AD INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ADSTAT

ÁÁÁÁ

P072

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A/D Conversion Data Register

ÁÁÁÁ

ADDATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P073

P07C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P07D

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Data Input Register

ÁÁÁÁ

ADIN

ÁÁÁÁ

P07E

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Input Enable Register

ÁÁÁÁ

ADENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P07F

AD STEST

PRIORITY

AD ESPEN

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ADPRI

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C

FEBRUAR

1990 REVISED FEBRUAR

1997

POST

OFFICE BOX 1443 HOUST

ON,

TEXAS

772511443

Table 15. TMS370 Family Opcode/Instruction Map

MSN

JMP

#ra
2/7

INCW

#ra,Rd

3/11

MOV

Ps,A

2/8

CLRC /

TST A

1/9

MOV

A,B

1/9

MOV
A,Rd

2/7

TRAP

1/14

LDST

2/6

2/5

MOV

A,Pd

2/8

MOV

B,Pd

2/8

MOV

Rs,Pd

3/10

MOV

Ps,B

2/7

MOV
B,Rd

2/7

TRAP

1/14

MOV

#ra[SP],A

2/7

2/5

MOV

Rs,A

2/7

MOV

#n,A

2/6

MOV

Rs,B

2/7

MOV

Rs,Rd

3/9

MOV

#n,B

2/6

MOV

B,A

1/8

MOV

#n,Rd

3/8

MOV

Ps,Rd

3/10

DEC

1/8

DEC

1/8

DEC

2/6

TRAP

1/14

MOV

A,*ra[SP]

2/7

2/5

AND
Rs,A

2/7

AND
#n,A

2/6

AND
Rs,B

2/7

AND

Rs,Rd

3/9

AND
#n,B

2/6

AND

B,A

1/8

AND

#n,Rd

3/8

AND
A,Pd

2/9

AND
B,Pd

2/9

AND

#n,Pd

3/10

INC

1/8

INC

1/8

INC

2/6

TRAP

1/14

CMP

*n[SP],A

2/8

2/5

Rs,A

2/7

#n,A

2/6

Rs,B

2/7

Rs,Rd

3/9

#n,B

2/6

B,A

1/8

#n,Rd

3/8

A,Pd

2/9

B,Pd

2/9

#n,Pd

3/10

INV

1/8

INV

1/8

INV

2/6

TRAP

1/14

extend

inst,2

opcodes

S
N

JPZ

2/5

XOR
Rs,A

2/7

XOR

#n,A

2/6

XOR
Rs,B

2/7

XOR

Rs,Rd

3/9

XOR

#n,B

2/6

XOR

B,A

1/8

XOR

#n,Rd

3/8

XOR
A,Pd

2/9

XOR
B,Pd

2/9

XOR

#n,Pd

3/10

CLR

1/8

CLR

1/8

CLR

2/6

TRAP

1/14

JNZ

2/5

BTJO

Rs,A,ra

3/9

BTJO

#n,A,ra

3/8

BTJO

Rs,B,ra

3/9

BTJO

Rs,Rd,ra

4/11

BTJO

#n,B,ra

3/8

BTJO

B,A,ra

2/10

BTJO

#n,Rd,ra

4/10

BTJO

A,Pd,ra

3/11

BTJO

B,Pd,ra

3/10

BTJO

#n,Pd,ra

4/11

XCHB

1/10

XCHB A /

TST B

1/10

XCHB

2/8

TRAP

1/14

IDLE

1/6

JNC

2/5

BTJZ

Rs.,A,ra

3/9

BTJZ

#n,A,ra

3/8

BTJZ

Rs,B,ra

3/9

BTJZ

Rs,Rd,ra

4/11

BTJZ

#n,B,ra

3/8

BTJZ

B,A,ra

2/10

BTJZ

#n,Rd,ra

4/10

BTJZ

A,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

BTJZ

#n,Pd,ra

4/11

SWAP

1/11

SWAP

1/11

SWAP

2/9

TRAP

1/14

MOV

#n,Pd

3/10

2/5

ADD
Rs,A

2/7

ADD
#n,A

2/6

ADD
Rs,B

2/7

ADD

Rs,Rd

3/9

ADD
#n,B

2/6

ADD

B,A

1/8

ADD

#n,Rd

3/8

MOVW
#16,Rd

4/13

MOVW

Rs,Rd

3/12

MOVW

#16[B],Rpd

4/15

PUSH

1/9

PUSH

1/9

PUSH

2/7

TRAP

1/14

SETC

1/7

2/5

ADC
Rs,A

2/7

ADC
#n,A

2/6

ADC
Rs,B

2/7

ADC

Rs,Rd

3/9

ADC
#n,B

2/6

ADC

B,A

1/8

ADC

#n,Rd

3/8

JMPL

lab
3/9

JMPL

*Rp

2/8

JMPL

*lab[B]

3/11

POP

1/9

POP

1/9

POP

2/7

TRAP

1/14

RTS

1/9

JLE

2/5

SUB

Rs,A

2/7

SUB
#n,A

2/6

SUB

Rs,B

2/7

SUB

Rs,Rd

3/9

SUB
#n,B

2/6

SUB

B,A

1/8

SUB

#n,Rd

3/8

MOV

& lab,A

3/10

MOV

*Rp,A

2/9

MOV

*lab[B],A

3/12

DJNZ

A,#ra

2/10

DJNZ

B,#ra

2/10

DJNZ

Rd,#ra

3/8

TRAP

1/14

RTI

1/12

JHS

2/5

SBB

Rs,A

2/7

SBB
#n,A

2/6

SBB

Rs,B

2/7

SBB

Rs,Rd

3/9

SBB
#n,B

2/6

SBB

B,A

1/8

SBB

#n,Rd

3/8

MOV

A, & lab

3/10

MOV

A, *Rp

2/9

MOV

A,*lab[B]

3/12

COMPL

1/8

COMPL

1/8

COMPL

2/6

TRAP

1/14

PUSH

1/8

All conditional jumps (opcodes 01 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ

instructions have a relative address as the last operand.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C

FEBRUAR

1990 REVISED FEBRUAR

1997

emp

l
ate

l
ease

ate:

POST

OFFICE BOX 1443 HOUST

ON,

TEXAS

772511443

Table 15. TMS370 Family Opcode/Instruction Map

(Continued)

MSN

JNV

2/5

MPY
Rs,A

2/46

MPY

#n,A

2/45

MPY
Rs,B

2/46

MPY

Rs,Rd

3/48

MPY

#n,B

2/45

MPY

B,A

1/47

MPY

#n,Rs

3/47

BR
lab
3/9

*Rp

2/8

*lab[B]

3/11

1/8

2/6

TRAP

1/14

POP

1/8

JGE

2/5

CMP
Rs,A

2/7

CMP

#n,A

2/6

CMP
Rs,B

2/7

CMP

Rs,Rd

3/9

CMP

#n,B

2/6

CMP

B,A

1/8

CMP

#n,Rd

3/8

CMP

& lab,A

3/11

CMP

*Rp,A

2/10

CMP

*lab[B],A

3/13

RRC

1/8

RRC

1/8

RRC

2/6

TRAP

1/14

LDSP

1/7

S
N

2/5

DAC
Rs,A

2/9

DAC
#n,A

2/8

DAC
Rs,B

2/9

DAC

Rs,Rd

3/11

DAC
#n,B

2/8

DAC

B,A

1/10

DAC

#n,Rd

3/10

CALL

lab

3/13

CALL

*Rp

2/12

CALL

*lab[B]

3/15

1/8

RL
Rd

2/6

TRAP

1/14

STSP

1/8

JLO

2/5

DSB

Rs,A

2/9

DSB
#n,A

2/8

DSB

Rs,B

2/9

DSB

Rs,Rd

3/11

DSB
#n,B

2/8

DSB

B,A

1/10

DSB

#n,Rd

3/10

CALLR

lab

3/15

CALLR

*Rp

2/14

CALLR

*lab[B]

3/17

RLC

1/8

RLC

1/8

RLC

2/6

TRAP

1/14

NOP

1/7

Second byte of two-byte instructions (F4xx):

MOVW

*n[Rn]

4/15

DIV

Rn.A

3/14-63

JMPL

*n[Rn]

4/16

Legend:
*

= Indirect addressing operand prefix

= Direct addressing operand prefix

MOV

*n[Rn],A

4/17

= immediate operand

#16 = immediate 16-bit number
lab = 16-label

di t 8 bit

MOV

A,*n[Rn]

4/16

= immediate 8-bit number

Pd = Peripheral register containing destination type
Pn = Peripheral register
Ps = Peripheral register containing source byte

*n[Rn]

4/16

Ps = Peri heral register containing source byte
ra

= Relative address

Rd = Register containing destination type
Rn = Register file

CMP

*n[Rn],A

4/18

Rp = Register pair
Rpd = Destination register pair
Rps = Source Register pair

CALL

*n[Rn]

4/20

Rs = Register containing source byte

CALLR

*n[Rn]

4/22

All conditional jumps (opcodes 01 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ

instructions have a relative address as the last operand.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

development system support

The TMS370 family development support tools include an assembler, a C-compiler, a linker, a starter kit, CDT
and an EEPROM / UVEPROM programmer.

Assembler / linker (Part No. TMDS374085002 for PC)

Includes extensive macro capability

Provides high-speed operation

Includes format conversion utilities for popular formats

ANSI C Compiler (Part No. TMDS374085502 for PC, Part No. TMDS374055509 for HP700

, Sun-3

or Sun-4

)

Generate assembly code for the TMS370 that can be inspected easily

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct reference to the TMS370's port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (Compact Development Tool) PACT real-time in-circuit emulation

Base (Part Number EDSCDT37P for PC, requires cable)

Cable for 44-pin PLCC (Part No. EDSTRG44PLCC32)

EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Includes compatibility to upload / download program and data memory

Execute programs and software routines

Includes 1 024-sample trace buffer

Includes single-step executable instructions

Uses software breakpoints to halt program execution at selected address

Microcontroller programmer

Base (Part No. TMDS3760500A for PC, requires programmer head)

Single unit head for 44-pin PLCC (Part No. TMDS3780510A)

PC-based, window / function-key-oriented user interface for ease of use and rapid learning environment

Starter Kit (Part No. TMDS37000 For PC)

Includes TMS370 Assembler diskette and documentation

Includes TMS370 Simulator

Includes programming adapter board and programming software

Does not include (to be supplied by the user):

+ 5 V power supply

ZIF sockets

9-pin RS-232 cable

HP700 is a trademark of Hewlett-Packard Company.
Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

new code release form

Figure 8 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

TMS370 MICROCONTROLLER PRODUCTS

DATE:

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
2. An attached specification if not using TI standard specification as incorporated in TI's applicable device data book.

Company Name:
Street Address:
Street Address:
City:

State

Zip

Contact Mr./Ms.:
Phone: (

)

Ext.:

Customer Purchase Order Number:

Customer Part Number:
Customer Application:

Customer Print Number *Yes:

No:

(Std. spec to be followed)

*If Yes: Customer must provide "print" to TI w/NCRF for approval before ROM
code processing starts.

TMS370 Device:

TI Customer ROM Number:
(provided by Texas Instruments)

CONTACT OPTIONS FOR THE 'A' VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

Low Power Modes
[] Enabled
[] Disabled

Watchdog counter
[] Standard
[] Hard Enabled
[] Simple Counter

Clock Type
[] Standard (/4)
[] PLL (/1)

[] Supply Voltage MIN:

MAX:

(std range: 4.5V to 5.5V)

NOTE:
Non 'A' version ROM devices of the TMS370 microcontrollers will have the
"Low-power modes Enabled", "Divide-by-4" Clock, and "Standard" Watchdog
options. See the

TMS370 Family User's Guide (literature number SPNU127)

or the

TMS370 Family Data Manual (literature number SPNS014B).

TEMPERATURE RANGE

[] 'L':

to 70

C (standard)

[] 'A':

to 85

[] 'T':

to 105

PACKAGE TYPE

[] 'N' 28-pin PDIP

[] "FN" 44-pin PLCC

[] "FN" 28-pin PLCC

[] "FN" 68-pin PLCC

[] "N" 40-pin PDIP

[] "NM" 64-pin PSDIP

[] "NJ" 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization
[] TI standard w/customer part number
[] Customer symbolization

(per attached spec, subject to approval)

[] YES

[] NO

NON-STANDARD SPECIFICATIONS:
ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a 'P' in the symbolization preceding the
TI part number.

RELEASE AUTHORIZATION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:
Prod. Eng.:
Proto. Release:

Figure 8. Sample New Code Release Form

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Table 17 is a collection of all the peripheral file frames used in the 'Cx32 (provided for a quick reference).

Table 17. Peripheral File Frame Compilation

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System Configuration Registers

ÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

BIT 5

ÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁ

REG

ÁÁÁ

P010

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

OSC FLT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MC PIN

WPO

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

MC PIN

DATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

P /

MODE

ÁÁÁ

SCCR0

ÁÁÁ

P011

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AUTO

WAIT

DISABLE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

MEMORY

DISABLE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

SCCR1

ÁÁÁ

P012

HALT /

STANDBY

PWRDWN /

IDLE

BUS

STEST

CPU

STEST

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT1

NMI

PRIVILEGE

DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

P013

P016

Reserved

ÁÁÁ

P017

ÁÁÁÁ

INT1

FLAG

ÁÁÁÁÁ

INT1

PIN DATA

ÁÁÁÁ

ÁÁÁÁÁ

INT1

POLARITY

ÁÁÁÁ

INT1

PRIORITY

ÁÁÁÁÁ

INT1

ENABLE

ÁÁÁ

INT1

ÁÁÁ

P018

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT2

FLAG

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT2

PIN DATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT2

DATA DIR

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT2

DATA OUT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT2

POLARITY

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INT2

PRIORITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INT2

ENABLE

ÁÁÁ

INT2

ÁÁÁ

P019

ÁÁÁÁ

INT3

FLAG

ÁÁÁÁÁ

INT3

PIN DATA

ÁÁÁÁ

INT3

DATA DIR

ÁÁÁÁ

INT3

DATA OUT

ÁÁÁÁÁ

INT3

POLARITY

ÁÁÁÁ

INT3

PRIORITY

ÁÁÁÁÁ

INT3

ENABLE

ÁÁÁ

INT3

ÁÁÁ

P01A

ÁÁÁÁ

BUSY

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

W1W0

ÁÁÁÁÁ

EXE

ÁÁÁ

DEECTL

ÁÁÁ

P01B

Reserved

ÁÁÁ

P01C

ÁÁÁÁ

BUSY

ÁÁÁÁÁ

VPPS

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

EXE

ÁÁÁ

EPCTLL

ÁÁÁ

P01D

P01E

P01F

Reserved

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Digital Port Control Registers

ÁÁÁ

P020

Reserved

ÁÁÁ

APORT1

ÁÁÁ

P021

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Control Register 2 (must be 0)

ÁÁÁ

APORT2

ÁÁÁ

P022

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Data

ÁÁÁ

ADATA

ÁÁÁ

P023

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port A Direction

ÁÁÁ

ADIR

ÁÁÁ

P024

P02B

Reserved

ÁÁÁ

P02C

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Control Register 1

(must be 0)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Port D Control Register 1

(must be 0)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

DPORT1

ÁÁÁ

P02D

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Port D Control Register 2

(must be 0)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Port D Control Register 2

(must be 0)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

DPORT2

ÁÁÁ

P02E

ÁÁÁÁÁÁÁÁ

Port D Data

ÁÁÁÁ

ÁÁÁÁÁÁÁ

Port D Data

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

DDATA

ÁÁÁ

P02F

ÁÁÁÁÁÁÁÁ

Port D Direction

ÁÁÁÁ

ÁÁÁÁÁÁÁ

Port D Direction

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

DDIR

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT Module Register Memory Map

ÁÁÁ

P040

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

DEFTIM

OVRFL

INT ENA

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

DEFTIM

OVRFL

INT FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA ENA

FAST

MODE

SELECT

PACT

PRESCALE

SELECT3

PACT

PRESCALE

SELECT2

PACT

PRESCALE

SELECT1

PACT

PRESCALE

SELECT0

ÁÁÁ

PACTSCR

ÁÁÁ

P041

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

INT ENA

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMD/DEF

AREA

START BIT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CMD/DEF

AREA

START BIT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

CDSTART

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

To configure D3 as SYSCLK, set port D register 2 = 08h.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Table 17. Peripheral File Frame Compilation (Continued)

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

BIT 7

ÁÁÁÁ

BIT 6

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

REG

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PACT Module Register Memory Map (Continued)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P042

CMD/DEF

AREA

END BIT 6

CMD/DEF

AREA

END BIT 5

CMD/DEF

AREA

END BIT 4

CMD/DEF

AREA

END BIT 3

CMD/DEF

AREA END

BIT 2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CDEND

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P043

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 5

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

BUFFER

POINTER

BIT 4

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFFER

POINTER

BIT 1

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BUFPTR

ÁÁÁÁ

P044

Reserved

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P045

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT

RXRDY

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT

TXRDY

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT

PARITY

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT FE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT SCI

RX INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT SCI

TX INT ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT SCI SW

RESET

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

SCICTLP

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P046

PACT

RXDT7

PACT

RXDT6

PACT

RXDT5

PACT

RXDT4

PACT

RXDT3

PACT

RXDT2

PACT

RXDT1

PACT RXDT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

RXBUFP

ÁÁÁÁ

P047

ÁÁÁÁ

PACT

TXDT7

ÁÁÁÁ

PACT

TXDT6

ÁÁÁÁ

PACT

TXDT5

ÁÁÁÁÁ

PACT

TXDT4

ÁÁÁÁ

PACT

TXDT3

ÁÁÁÁ

PACT

TXDT2

ÁÁÁÁ

PACT

TXDT1

ÁÁÁÁÁ

PACT TXDT0

ÁÁÁÁ

TXBUFP

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P048

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP8

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP7

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP6

STATE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT OP5

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP4

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP3

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACT OP2

STATE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

PACT OP1

STATE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PSTATE

ÁÁÁÁ

P049

CMD/DEF

INT 7 FLAG

CMD/DEF

INT 6 FLAG

ÁÁÁÁ

CMD/DEF

INT 5 FLAG

ÁÁÁÁÁ

CMD/DEF

INT 4 FLAG

ÁÁÁÁ

CMD/DEF

INT 3 FLAG

ÁÁÁÁ

CMD/DEF

INT 2 FLAG

ÁÁÁÁ

CMD/DEF

INT 1 FLAG

ÁÁÁÁÁ

CMD/DEF INT

0 FLAG

ÁÁÁÁ

CDFLAGS

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P04A

CP2 INT

ENA

CP2 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP2 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP2 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP1 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP1 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P04B

CP4 INT

ENA

CP4 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP4 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP4 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP3 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP3 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P04C

CP6 INT

ENA

CP6 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP6 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP6 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 INT

ENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 INT

FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP5 CAPT

RISING

EDGE

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CP5 CAPT

FALLING

EDGE

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPCTL3

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P04D

BUFFER

HALF/FULL

INT ENA

BUFFER

HALF/FULL

INT FLAG

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 3

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

INPUT

CAPT

PRESCALE

SELECT 1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CP6

EVENT

ONLY

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

EVENT

COUNTER

SW RESET

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

OP/ SET/CLR

SELECT

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPPRE

ÁÁÁÁ

P04E

WATCHDOG RESET KEY

ÁÁÁÁ

WDRST

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P04F

PACT

STEST

PACT

SUSPEND

PACT

GROUP 1

PRIORITY

PACT

GROUP 2

PRIORITY

PACT

GROUP 3

PRIORITY

PACT

MODE

SELECT

PACT WD

PRESCALE

SELECT 1

PACT WD

PRESCALE

SELECT 0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

PACTPRI

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P070

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CONVERT

START

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

SAMPLE

START

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

REF VOLT

SELECT2

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

REF VOLT

SELECT1

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

REF VOLT

SELECT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD INPUT

SELECT2

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AD INPUT

SELECT1

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AD INPUT SE-

LECT0

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ADCTL

ÁÁÁÁ

P071

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

AD READY

ÁÁÁÁ

AD INT

FLAG

ÁÁÁÁÁ

AD INT ENA

ÁÁÁÁ

ADSTAT

ÁÁÁÁ

P072

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A/D Conversion Data Register

ÁÁÁÁ

ADDATA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P073

P07C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P07D

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Data Input Register

ÁÁÁÁ

ADIN

ÁÁÁÁ

P07E

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port E Input Enable Register

ÁÁÁÁ

ADENA

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

P07F

AD STEST

PRIORITY

AD ESPEN

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ADPRI

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range,V

CC1

(see Note 3)

0.6 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, All pins except MC

0.6 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.6 V to 14 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

0 or V

CC1

)

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

0 or V

CC1

)

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current per buffer, I

= 0 to V

CC1

) (see Note 4)

10 mA

. . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

current

170 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

current

170 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation

800 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature, T

: L version

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A version

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T version

C to 105

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

3. Unless otherwise noted, all voltage values are with respect to VSS1.
4. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in

any buffer can affect the levels on other buffers.

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC1

Supply voltage (see Note 3)

4.5

5.5

VCC1

RAM data retention supply voltage (see Note 5)

5.5

VCC3 Analog supply voltage (see Note 3)

4.5

5.5

VSS3

Analog supply ground

0.3

VIL

Low level input voltage

All pins except MC

VSS1

0.8

VIL

Low-level input voltage

MC, normal operation

VSS1

0.3

Hi h l

l i

All pins except MC, XTAL2 / CLKIN, and
RESET

VCC1

VIH

High-level input voltage

XTAL2 / CLKIN

0.8 VCC1

VCC1

RESET

0.7 VCC1

VCC1

EEPROM write protect override (WPO)

11.7

VMC

MC (mode control) voltage

EPROM programming voltage (VPP)

13.2

13.5

Microcomputer

VSS1

0.3

L version

Operating free-air temperature

A version

T version

105

NOTES:

3. Unless otherwise noted, all voltage values are with respect to VSS1.
5. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range.

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOL

Low-level output voltage

IOL = 1.4 mA

0.4

VOH

High level output voltage

IOH = 50

0.9 VCC1

VOH

High-level output voltage

IOH = 2 mA

2.4

0 V

0.3 V

Input current

0.3 V < VI

13 V

650

Input current

12 V

13 V

I / O pins

0 V

VCC1

IOL

Low-level output current

VOL = 0.4 V

1.4

IOH

High level output current

VOH = 0.9 VCC1

IOH

High-level output current

VOH = 2.4 V

See Notes 6 and 7

SYSCLK = 5 MHz

Supply current (operating mode)

See Notes 6 and 7

(

)

OSC POWER bit = 0

SYSCLK = 3 MHz

See Notes 6 and 7

SYSCLK = 0.5 MHz

See Notes 6 and 7

SYSCLK = 5 MHz

ICC1

Supply current (STANDBY mode)

See Notes 6 and 7

ICC1

(

)

OSC POWER bit = 0

SYSCLK = 3 MHz

See Notes 6 and 7

SYSCLK = 0.5 MHz

Supply current (STANDBY mode)

See Notes 6 and 7

SYSCLK = 3 MHz

8.6

(

)

OSC POWER bit = 1

See Notes 6 and 7

SYSCLK = 0.5 MHz

3.0

Supply current (HALT mode)

See Note 6

Supply current (HALT mode)

XTAL2/CLKIN < 0.2 V

Input current IPP will be a maximum of 50 mA only when programming EPROM.
NOTES:

6. Single chip mode, ports configured as inputs or outputs with no load. All inputs

0.2 V or

VCC 0.2V.

7. XTAL2/CLKIN is driven with an external square-wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance
in pF).

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

external clocking requirements for clock divided by 4 (see Note 8 and Figure 14)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 9)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall

100

CLKIN

Crystal operating frequency

MHz

SYSCLK

Internal system clock operating frequency

0.5

MHz

SYSCLK = CLKIN/4
NOTES:

8. For VIL and VIH, refer to recommended operating conditions.
9. This pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an

XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 14. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL) (see Note 8 and Figure 15)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 9)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise

100

CLKIN

Crystal operating frequency

MHz

SYSCLK

Internal system clock operating frequency

MHz

SYSCLK = CLKIN/1
NOTES:

8. For VIL and VIH, refer to recommended operating conditions.
9. This pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an

XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 15. External Clock Timing for Divide-by-1

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

switching characteristics and timing requirements

(see Note 10 and Figure 16)

NO.

PARAMETER

MIN

MAX

UNIT

Cycle time SYSCLK (system clock)

Divide-by-4

200

2000

Cycle time, SYSCLK (system clock)

Divide-by-1

200

500

tw(SCL)

Pulse duration, SYSCLK low

0.5 tc20

0.5 tc

tw(SCH)

Pulse duration, SYSCLK high

0.5 tc

0.5 tc + 20

NOTE 10:

c = system clock cycle time = 1 / SYSCLK

SYSCLK

Figure 16. SYSCLK Timing

general purpose output signal switching time requirements (see Figure 17)

MIN

NOM

MAX

UNIT

Rise time

Fall time

Figure 17. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN

MAX

UNIT

tw(PGM)B

Pulse duration, programming signal to ensure valid data is stored (byte mode)

tw(PGM)AR

Pulse duration, programming signal to ensure valid data is stored (array mode)

recommended EPROM operating conditions for programming

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.75

5.5

VPP

Supply voltage at MC pin

13.2

13.5

IPP

Supply current at MC pin during programming (VPP = 13 V)

SYSCLK

System clock

Divide-by-4

0.5

MHz

SYSCLK

System clock

Divide-by-1

MHz

recommended EPROM timing requirements for programming

MIN

NOM

MAX

UNIT

tw(EPGM)

Pulse duration, programming signal (see Note 11)

0.40

0.50

NOTE 11: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

ADC1 converter

The ADC1 converter has a separate power bus for its analog circuitry. These pins are referred to as V

CC3

and

SS3

. The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry

that can be present on V

SS1

and V

CC1

from coupling into the ADC1 analog stage. All ADC1 specifications are

given with respect to V

SS3

unless otherwise noted.

Resolution

8-bits (256 values)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monotonic

Yes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output conversion mode

00h to FFh (00 for V

SS3

; FF for V

ref

)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conversion time (excluding sample time)

164 t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC3 Analog supply voltage

4.5

5.5

VCC3 Analog supply voltage

VCC10.3

VCC1+0.3

VSS3

Analog ground

VSS10.3

VSS1+0.3

Vref

Non-VCC3 reference

2.5

VCC3

VCC3 + 0.1

Analog input for conversion

VSS3

Vref

Vref must be stable, within

1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over recommended ranges operating conditions

PARAMETER

MIN

MAX

UNIT

Absolute accuracy

VCC3 = 5.5 V

Vref = 5.1 V

1.5

LSB

Differential/integral linearity error§

VCC3 = 5.5 V

Vref = 5.1 V

0.9

LSB

ICC3

Analog supply current

Converting

ICC3

Analog supply current

Nonconverting

Input current, AN0 AN7

0 V

5.5 V

Iref

Input charge current

Z f

Source impedance of V f

SYSCLK

3 MHz

Zref

Source impedance of Vref

3 MHz < SYSCLK

5 MHz

Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and

differential/integral linearity errors in terms of LSBs increase.

§ Excluding quantization error of 1/2 LSB

TMS370Cx32
8-BIT MICROCONTROLLER

SPNS015C FEBRUARY 1990 REVISED FEBRUARY 1997

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

ADC1 converter (continued)

The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the
sample time is user-defined so that the high-impedance can be accommodated without penalty to the
low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register
(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START,
ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE START and CONVERT START bits,
signaling that a conversion has started and that the analog signal can be removed.

analog timing requirements (see Figure 18)

MIN

MAX

UNIT

tsu(S)

Setup time, analog to sample command

th(AN)

Hold time, analog input from start of conversion

18tc

tw(S)

Pulse duration, sample time per kilo-

of source impedance

s / k

The value given is valid for a signal with a source impedance > 1 k

. If the source impedance is < 1 k

, use a minimum sampling time of 1

Analog In

Sample Start

Convert Start

Analog Stable

th(AN)

tw(S)

tsu(S)

Figure 18. Analog Timing

Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.

Table 18. TMS370Cx32 Family Package Type and Mechanical Cross-Reference

ÁÁÁÁÁÁÁ

PKG TYPE

(mil pin spacing)

ÁÁÁÁÁÁÁÁÁÁ

TMS370 GENERIC NAME

ÁÁÁÁÁÁÁÁÁÁÁÁ

PKG TYPE NO. AND

MECHANICAL NAME

ÁÁÁÁÁÁÁÁ

DEVICE PART NUMBERS

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

FN 44 pin
(50-mil pin spacing)

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

PLASTIC LEADED CHIP CARRIER
(PLCC)

ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

FN(S-PQCC-J**) PLASTIC J-LEADED
CHIP CARRIER

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TMS370C032AFNA
TMS370C032AFNL
TMS370C032AFNT
TMS370C332AFNA
TMS370C332AFNL
TMS370C332AFNT
TMS370C732AFNT

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

FZ 44 pin
(50-mil pin spacing)

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CERAMIC LEADED CHIP CARRIER
(CLCC)

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FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER

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SE370C732AFZT

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Part Number TMS370Cx32