TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
Data Manual
Literature Number: SPRS230F
October 2003 Revised September 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Contents
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F OCTOBER 2003 REVISED SEPTEMBER 2005
Revision History
...........................................................................................................................
8
1
Features
............................................................................................................................
11
2
Introduction
.......................................................................................................................
12
2.1
Pin Assignments
............................................................................................................
13
2.2
Signal Descriptions
.........................................................................................................
16
3
Functional Overview
...........................................................................................................
22
3.1
Memory Map
................................................................................................................
23
3.2
Brief Descriptions
...........................................................................................................
27
3.2.1
C28x CPU
.......................................................................................................
27
3.2.2
Memory Bus (Harvard Bus Architecture)
....................................................................
28
3.2.3
Peripheral Bus
..................................................................................................
28
3.2.4
Real-Time JTAG and Analysis
................................................................................
28
3.2.5
Flash
..............................................................................................................
28
3.2.6
M0, M1 SARAMs
...............................................................................................
29
3.2.7
L0, L1, H0 SARAMs
............................................................................................
29
3.2.8
Boot ROM
........................................................................................................
29
3.2.9
Security
..........................................................................................................
30
3.2.10
Peripheral Interrupt Expansion (PIE) Block
..................................................................
31
3.2.11
External Interrupts (XINT1, XINT2, XNMI)
...................................................................
31
3.2.12
Oscillator and PLL
..............................................................................................
31
3.2.13
Watchdog
........................................................................................................
31
3.2.14
Peripheral Clocking
.............................................................................................
31
3.2.15
Low-Power Modes
..............................................................................................
31
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
..............................................................................
32
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
.........................................................
32
3.2.18
32-Bit CPU-Timers (0, 1, 2)
...................................................................................
32
3.2.19
Control Peripherals
.............................................................................................
32
3.2.20
Serial Port Peripherals
.........................................................................................
33
3.3
Register Map
................................................................................................................
33
3.4
Device Emulation Registers
...............................................................................................
36
3.5
Interrupts
....................................................................................................................
37
3.5.1
External Interrupts
..............................................................................................
39
3.6
System Control
.............................................................................................................
40
3.6.1
OSC and PLL Block
............................................................................................
41
3.6.2
Watchdog Block
.................................................................................................
44
3.7
Low-Power Modes Block
..................................................................................................
45
4
Peripherals
........................................................................................................................
46
4.1
32-Bit CPU-Timers 0/1/2
..................................................................................................
46
4.2
Enhanced PWM Modules (ePWM1/2/3/4/5/6)
..........................................................................
48
4.3
Hi-Resolution PWM (HRPWM)
...........................................................................................
50
4.4
Enhanced CAP Modules (eCAP1/2/3/4)
................................................................................
51
4.5
Enhanced QEP Modules (eQEP1/2)
.....................................................................................
53
4.6
Enhanced Analog-to-Digital Converter (ADC) Module
................................................................
55
4.7
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
.....................................
60
4.8
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
....................................................
65
4.9
Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
...........................................
68
4.10
Inter-Integrated Circuit (I
2
C)
...............................................................................................
72
4.11
GPIO MUX
..................................................................................................................
74
5
Device Support
..................................................................................................................
78
5.1
Device and Development Support Tool Nomenclature
................................................................
78
2
Contents
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TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F OCTOBER 2003 REVISED SEPTEMBER 2005
5.2
Documentation Support
...................................................................................................
79
6
Electrical Specifications
......................................................................................................
82
6.1
Absolute Maximum Ratings
...............................................................................................
82
6.2
Recommended Operating Conditions
...................................................................................
82
6.3
Electrical Characteristics
.................................................................................................
83
6.4
Current Consumption
.....................................................................................................
83
6.4.1
Reducing Current Consumption
..............................................................................
85
6.4.2
Current Consumption Graphs
..................................................................................
86
6.5
Timing Parameter Symbology
............................................................................................
87
6.5.1
General Notes on Timing Parameters
........................................................................
87
6.5.2
Test Load Circuit
................................................................................................
88
6.5.3
Device Clock Table
.............................................................................................
88
6.6
Clock Requirements and Characteristics
...............................................................................
89
6.7
Power Sequencing
.........................................................................................................
90
6.7.1
Power Management and Supervisory Circuit Solutions
....................................................
90
6.8
General-Purpose Input/Output (GPIO)
..................................................................................
93
6.8.1
GPIO - Output Timing
...........................................................................................
93
6.8.2
GPIO - Input Timing
.............................................................................................
94
6.9
Enhanced Control Peripherals
............................................................................................
99
6.9.1
Enhanced Pulse Width Modulator (ePWM) Timing
.........................................................
99
6.9.3
External Interrupt Timing
.................................................................................................
101
6.9.4
I2C Electrical Specification and Timing
................................................................................
102
6.9.5
Serial Peripheral Interface (SPI) Master Mode Timing
..............................................................
102
6.9.6
SPI Slave Mode Timing
..................................................................................................
106
6.9.7
On-Chip Analog-to-Digital Converter
...................................................................................
109
6.9.7.1
ADC Power-Up Control Bit Timing
..........................................................................
110
6.9.7.2
Definitions
......................................................................................................
111
6.9.7.3
Sequential Sampling Mode (Single-Channel) (SMODE = 0)
............................................
112
6.9.7.4
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
...........................................
113
6.10
Detailed Descriptions
....................................................................................................
114
6.11
Flash Timing
...............................................................................................................
115
7
Mechanical Data
...............................................................................................................
117
Contents
3
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TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F OCTOBER 2003 REVISED SEPTEMBER 2005
List of Figures
2-1
TMS320F2808 100-Pin PZ LQFP (Top View)
.................................................................................
13
2-2
TMS320F2806 100-Pin PZ LQFP (Top View)
.................................................................................
14
2-3
TMS320F2801/UCD9501 100-Pin PZ LQFP (Top View)
....................................................................
15
2-4
TMS320F280x 100-Ball GGM and ZGM MicroStarTM BGA (Bottom View)
...............................................
16
3-1
Functional Block Diagram
........................................................................................................
22
3-2
F2808 Memory Map
..............................................................................................................
23
3-3
F2806 Memory Map
..............................................................................................................
24
3-4
F2801/9501 Memory Map
........................................................................................................
25
3-5
External and PIE Interrupt Sources
.............................................................................................
37
3-6
Multiplexing of Interrupts Using the PIE Block
................................................................................
38
3-7
Clock and Reset Domains
.......................................................................................................
40
3-8
OSC and PLL Block Diagram
...................................................................................................
41
3-9
Using a 3.3-V External Oscillator
...............................................................................................
42
3-10
Using a 1.8-V External Oscillator
...............................................................................................
42
3-11
Using the Internal Oscillator
.....................................................................................................
42
3-12
Watchdog Module
.................................................................................................................
44
4-1
CPU-Timers
........................................................................................................................
46
4-2
CPU-Timer Interrupt Signals and Output Signal
..............................................................................
47
4-3
Multiple PWM Modules in a 280x System
.....................................................................................
48
4-4
ePWM Sub-modules Showing Critical Internal Signal Interconects
........................................................
50
4-5
eCAP Functional Block Diagram
................................................................................................
51
4-6
eQEP Functional Block Diagram
................................................................................................
53
4-7
Block Diagram of the ADC Module
.............................................................................................
56
4-8
ADC Pin Connections With Internal Reference
...............................................................................
57
4-9
ADC Pin Connections With External Reference
..............................................................................
58
4-10
eCAN Block Diagram and Interface Circuit
....................................................................................
61
4-11
eCAN-A Memory Map
............................................................................................................
62
4-12
eCAN-B Memory Map
............................................................................................................
63
4-13
Serial Communications Interface (SCI) Module Block Diagram
............................................................
67
4-14
SPI Module Block Diagram (Slave Mode)
.....................................................................................
71
4-15
I
2
C Peripheral Module Interfaces
...............................................................................................
73
4-16
GPIO MUX Block Diagram
.......................................................................................................
74
4-17
Qualification Using Sampling Window
..........................................................................................
77
5-1
Example of TMS320x280x Device Nomenclature
............................................................................
79
5-2
Example of UCD Device Nomenclature
........................................................................................
79
6-1
Typical Operational Current Versus Frequency (F2808)
....................................................................
86
6-2
Typical Operational Power Versus Frequency (F2808)
......................................................................
87
6-3
3.3-V Test Load Circuit
...........................................................................................................
88
6-4
Clock Timing
.......................................................................................................................
90
4
List of Figures
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F OCTOBER 2003 REVISED SEPTEMBER 2005
6-5
Power-on Reset
...................................................................................................................
91
6-6
Warm Reset
........................................................................................................................
92
6-7
Example of Effect of Writing Into PLLCR Register
...........................................................................
93
6-8
General-Purpose Output Timing
................................................................................................
93
6-9
Sampling Mode
....................................................................................................................
94
6-10
General-Purpose Input Timing
..................................................................................................
95
6-11
IDLE Entry and Exit Timing
......................................................................................................
96
6-12
STANDBY Entry and Exit Timing Diagram
....................................................................................
97
6-13
HALT Wake Up Using GPIOn
...................................................................................................
98
6-14
PWM Hi-Z Characteristics
.......................................................................................................
99
6-15
ADCSOCAO or ADCSOCBO Timing
.........................................................................................
101
6-16
External Interrupt Timing
.......................................................................................................
101
6-17
SPI Master Mode External Timing (Clock Phase = 0)
......................................................................
104
6-18
SPI Master External Timing (Clock Phase = 1)
..............................................................................
106
6-19
SPI Slave Mode External Timing (Clock Phase = 0)
........................................................................
107
6-20
SPI Slave Mode External Timing (Clock Phase = 1)
........................................................................
108
6-21
ADC Power-Up Control Bit Timing
............................................................................................
110
6-22
ADC Analog Input Impedance Model
.........................................................................................
111
6-23
Sequential Sampling Mode (Single-Channel) Timing
.......................................................................
112
6-24
Simultaneous Sampling Mode Timing
........................................................................................
113
List of Figures
5
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