Document Outline

• Title Page - SPRS222C
• IMPORTANT NOTICE
• Revision History
• Contents
• List of Figures
• List of Tables
• 1 Device Overview
  • 1.1 Features
  • 1.2 Description
  • 1.3 Device Characteristics
  • 1.4 Device Compatibility
  • 1.5 Functional Block Diagram
  • 1.6 CPU (DSP Core) Description
    • 1.6.1 CPU Core Registers
  • 1.7 Memory Map Summary
    • 1.7.1 L2 Architecture Expanded
  • 1.8 Bootmode
  • 1.9 Pin Assignments
    • 1.9.1 Pin Map
    • 1.9.2 Signal Groups Description
    • 1.9.3 Terminal Functions
  • 1.10 Development
    • 1.10.1 Development Support
    • 1.10.2 Device Support
      • 1.10.2.1 Device and Development-Support Tool Nomenclature
      • 1.10.2.2 Documentation Support
      • 1.10.2.3 Device Silicon Revision
• 2 Device Configurations
  • 2.1 Configurations at Reset
    • 2.1.1 Peripheral Selection at Device Reset
    • 2.1.2 Device Configuration at Device Reset
  • 2.2 Configurations After Reset
    • 2.2.1 Peripheral Selection After Device Reset
  • 2.3 Peripheral Configuration Lock
  • 2.4 Device Status Register Description
  • 2.5 Multiplexed Pin Configurations
  • 2.6 Debugging Considerations
  • 2.7 Configuration Examples
• 3 Device Operating Conditions
  • 3.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)�
  • 3.2 Recommended Operating Conditions
  • 3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature ( Unless Otherwise Noted)
• 4 DM641/DM640 Peripheral Information and Electrical Specifications
  • 4.1 Parameter Information
    • 4.1.1 Parameter Information Device-Specific Information
      • 4.1.1.1 Signal Transition Levels
      • 4.1.1.2 Signal Transition Rates
      • 4.1.1.3 Timing Parameters and Board Routing Analysis
  • 4.2 Recommended Clock and Control Signal Transition Behavior
  • 4.3 Power Supplies
    • 4.3.1 Power-Supply Sequencing
    • 4.3.2 Power-Supply Design Considerations
    • 4.3.3 Power-Supply Decoupling
    • 4.3.4 Peripheral Power-Down Operation
    • 4.3.5 Power-Down Modes Logic
    • 4.3.6 Triggering, Wake-up, and Effects
    • 4.3.7 C64x Power-Down Mode with an Emulator
  • 4.4 Enhanced Direct Memory Access (EDMA) Controller
    • 4.4.1 EDMA Device-Specific Information
      • 4.4.1.1 EDMA Channel Synchronization Events
    • 4.4.2 EDMA Peripheral Register Description(s)
  • 4.5 Interrupts
    • 4.5.1 Interrupt Sources and Interrupt Selector
    • 4.5.2 Interrupts Peripheral Register Description(s)
    • 4.5.3 External Interrupts Electrical Data/Timing
  • 4.6 Reset
    • 4.6.1 Reset Electrical Data/Timing
  • 4.7 Clock PLL
    • 4.7.1 Clock PLL Device-Specific Information
    • 4.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)
  • 4.8 External Memory Interface (EMIIF)
    • 4.8.1 EMIF Device-Specific Information
    • 4.8.2 EMIF Peripheral Register Description(s)
    • 4.8.3 EMIF Electrical Data/Timing
      • 4.8.3.1 Asynchronous Memory Timing
      • 4.8.3.2 Programmable Synchronous Interface Timing
      • 4.8.3.3 Synchronous DRAM Timing
      • 4.8.3.4 HOLD\/HOLDA\ Timing
      • 4.8.3.5 BUSREQ Timing
  • 4.9 Multichannel Audio Serial Port (McASP0) Peripheral
    • 4.9.1 McASP0 Device-Specific Information
      • 4.9.1.1 McASP Block Diagram
    • 4.9.2 McASP0 Peripheral Register Description(s)
    • 4.9.3 McASP0 Electrical Data/Timing
      • 4.9.3.1 Multichannel Audio Serial Port (McASP) Timing
  • 4.10 Inter-Integrated Circuit (I2C)
    • 4.10.1 I2C Device-Specific Information
    • 4.10.2 I2C Peripheral Register Description(s)
    • 4.10.3 I2C Electrical Data/Timing
      • 4.10.3.1 Inter-Integrated Circuits (I2C) Timing
  • 4.11 Host-Port Interface (HPI) [DM641 Only]
    • 4.11.1 HPI Peripheral Register Description(s) [DM641 Only]
    • 4.11.2 Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only]
  • 4.12 Multichannel Buffered Serial Port (McBSP)
    • 4.12.1 McBSP Peripheral Register Description(s)
    • 4.12.2 McBSP Electrical Data/Timing
      • 4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing
  • 4.13 Video Port
    • 4.13.1 Video Port Device-Specific Information
    • 4.13.2 Video Port Peripheral Register Description(s)
    • 4.13.3 Video Port
      • 4.13.3.1 VCLKIN Timing (Video Capture Mode)
      • 4.13.3.2 Video Data and Control Timing (Video Capture Mode)
      • 4.13.3.3 VCLKIN Timing (Video Display Mode)
      • 4.13.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx ( Video Display Mode)
      • 4.13.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
  • 4.14 VCXO Interpolated Control (VIC)
    • 4.14.1 VIC Device-Specific Information
    • 4.14.2 VIC Peripheral Register Description(s)
    • 4.14.3 VIC Electrical Data/Timing
      • 4.14.3.1 STCLK Timing
  • 4.15 Ethernet Media Access Controller (EMAC)
    • 4.15.1 EMAC Device-Specific Information
    • 4.15.2 EMAC Peripheral Register Description(s)
    • 4.15.3 EMAC Electrical Data/Timing
  • 4.16 Management Data Input/Output (MDIO)
    • 4.16.1 Device-Specific Information
    • 4.16.2 Peripheral Register Description(s)
    • 4.16.3 Management Data Input/Output (MDIO) Electrical Data/Timing
  • 4.17 Timer
    • 4.17.1 Timer Device-Specific Information
    • 4.17.2 Timer Peripheral Register Description(s)
    • 4.17.3 Timer Electrical Data/Timing
  • 4.18 General-Purpose Input/Output (GPIO)
    • 4.18.1 GPIO Device-Specific Information
    • 4.18.2 GPIO Peripheral Register Description(s)
    • 4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing
  • 4.19 JTAG
    • 4.19.1 JTAG Device-Specific Information
      • 4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement
      • 4.19.1.2 JTAG ID Register Description
    • 4.19.2 JTAG Peripheral Register Description(s)
    • 4.19.3 JTAG Test-Port Electrical Data/Timing
• 5 Mechanical Data
  • 5.1 Thermal Data