TMS320C6201, TMS320C6201B

DIGITAL SIGNAL PROCESSORS

SPRS051F JANUARY 1997 REVISED AUGUST 1999

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201
6-, 5-ns Instruction Cycle Time
167-, 200-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
1336, 1 600 MIPS

Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201B
5-, 4.3-ns Instruction Cycle Time
200-, and 233-MHz Clock Rates
Eight 32-Bit Instructions/Cycle
1600, 1 860 MIPS

VelociTI

Advanced Very Long Instruction

Word (VLIW) 'C62x CPU Core
Eight Independent Functional Units:

Six ALUs (32-/40-Bit)
Two 16-Bit Multipliers (32-Bit Results)

 Load-Store Architecture With 32 32-Bit

General-Purpose Registers

Instruction Packing Reduces Code Size
All Instructions Conditional

Instruction Set Features
Byte-Addressable (8-, 16-, 32-Bit Data)
32-Bit Address Range
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization

1M-Bit On-Chip SRAM
512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

 512K-Bit Dual-Access Internal Data

(64K Bytes) Organized as a Single Block
('6201)

 512K-Bit Dual-Access Internal Data

(64K Bytes) Organized as Two Blocks for
Improved Concurrency ('6201B)

32-Bit External Memory Interface (EMIF)
Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

 Glueless Interface to Asynchronous

Memories: SRAM and EPROM

Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel

16-Bit Host-Port Interface (HPI)
Access to Entire Memory Map

Two Multichannel Buffered Serial Ports
(McBSPs)
Direct Interface to T1/E1, MVIP, SCSA

Framers

ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial Peripheral Interface (SPI)

Compatible (Motorola

)

Two 32-Bit General-Purpose Timers

Flexible Phase-Locked Loop (PLL) Clock
Generator

IEEE-1149.1 (JTAG

) Boundary-Scan

Compatible

352-Pin BGA Package (GGP Suffix) ('6201)

352-Pin BGA Package (GJC Suffix) ('6201B)

352-Pin BGA Package (GJL Suffix) ('6201B)

CMOS Technology
0.25-

m/5-Level Metal Process ('6201)

 0.18-

m/5-Level Metal Process ('6201B)

3.3-V I/Os, 2.5-V Internal ('6201)

3.3-V I/Os, 1.8-V Internal ('6201B)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

GJC/GJL/GGP

352-PIN BALL GRID ARRAY (BGA) PACKAGES

(BOTTOM VIEW)

AB
AA

B
A

TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS

SPRS051F JANUARY 1997 REVISED AUGUST 1999

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

description

The TMS320C62x

DSPs (including the TMS320C6201 and the TMS320C6201B devices) are the fixed-point

DSP family in the TMS320C6000 platform. The TMS320C6201 ('C6201) and the TMS320C6201B ('C6201B)
devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI

), making these DSPs an excellent choice for multichannel and

multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate
of 200 MHz, the 'C6201 offers cost-effective solutions to high-performance DSP programming challenges. The
'C6201B is a newer revision of the 'C6201 with performance of up to 1860 MIPS at a clock rate of 233 MHz.
The 'C6201/'C6201B DSPs possess the operational flexibility of high-speed controllers and the numerical
capability of array processors. Each of these processors have 32 general-purpose registers of 32-bit word
length and eight highly independent functional units. The eight functional units provide six arithmetic logic units
(ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. Both the 'C6201 and the
'C6201B can produce two multiply-accumulates (MACs) per cycle--for a total of 400 million MACs per second
(MMACS) for the 'C6201, and a total of 466 MMACS for the 'C6201B. The 'C62x DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The 'C6201/'C6201B includes a large bank of on-chip memory and has a powerful and diverse set of
peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or
memory-mapped program space. Data memory of the 'C6201 consists of a 64K-byte block of RAM, while data
memory of the 'C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set
includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface
(HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and
asynchronous peripherals.

The 'C62x has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows

debugger interface for visibility into source code

execution.

device characteristics

Table 1 provides an overview of the 'C62x DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

Table 1. Characteristics of the 'C6201/'C6201B Processors

CHARACTERISTICS

DESCRIPTION

Device Number

TMS320C6201

TMS320C6201B

On-Chip Memory

512-Kbit Program Memory
512-Kbit Data Memory (organized as a single block)

512-Kbit Program Memory
512-Kbit Data Memory (organized as two blocks)

Peripherals

2 Multichannel Buffered Serial Ports (McBSPs)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)

Cycle Time

5 ns (TMS320C6201-200),
6 ns (TMS320C6201-167)

4.3 ns (TMS320C6201B-233),
5 ns (TMS320C6201B-200)

Package Type

35 mm

35 mm, 352-Pin BGA (GGP)

35 mm

35 mm, 352-Pin BGA (GJC),

27 mm

27 mm, 352-Pin BGA (GJL)

Nominal Voltage

2.5 V Core
3.3 V I/O

1.8 V Core
3.3 V I/O

TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
Where unique device characteristics are specified, TMS320C6201 and TMS320C6201B identifiers are used. For generic characteristics, no

identifiers are needed, 'C62x is used, or 'C6000 is used.

TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS

SPRS051F JANUARY 1997 REVISED AUGUST 1999

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the 'C62x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units
on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features
a single data bus connected to all the registers on the other side, by which the two sets of functional units can
access data from the register files on the opposite side. While register access by functional units on the same
side of the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.

Another key feature of the 'C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
'C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least
significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous
execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch
packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.

TMS320C6201, TMS320C6201B

DIGITAL SIGNAL PROCESSORS

SPRS051F JANUARY 1997 REVISED AUGUST 1999

POST OFFICE BOX 1443

HOUSTON, TEXAS 772511443

CPU description (continued)

ÁÁ

'C62x CPU

ÁÁ

Program Memory

32-Bit Address

256-Bit Data

External Memory

Interface

Data Memory

32-Bit Address

8-, 16-, 32-Bit Data

Program Fetch

Instruction Dispatch

Instruction Decode

Data Path A

Register File A

Data Path B

Register File B

.L1

.S1

.M1 .D1

.D2

.M2 .S2

.L2

Control

Registers

Control

Logic

Test

Emulation

Interrupts

Additional

Peripherals:

Timers,

Serial Ports,

etc.

Figure 1. TMS320C62x CPU Block Diagram

Part Number TMS320C6201B