TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 SEPTEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

2 MSPS Max Throughput at 10 Bit (Single
Channel),

1 LSB DNL,

1 LSB INL MAX

3 MSPS Max Throughput at 8 Bit (Single
Channel),

1 LSB DNL,

1 LSB INL MAX

7 MSPS Max Throughput at 4 Bit (Single
Channel),

0.4 LSB DNL,

0.4 LSB INL MAX

No Missing Code for External Clock Up to
15 MHz at 5.5 V, 12 MHz at 2.7 V

ENOB 9.4 Bit, SINAD 57.8 dB, SFDR
70.8 dB, THD 68.8 dB, at fi = 800 kHz,
10 Bit

Wide Input Bandwidth for Undersampling
(75 MHz at 1 dB, >120 MHz at 3 dB) at
R

= 1 k

Software Programmable Power Down,
(1

A), Auto Powerdown (120

Single Wide Range Supply 2.7 VDC to
5.5 VDC

Low Supply Current 11 mA at 5.5 V, 10 MHz;
7 mA at 2.7 V, 8 MHz Operating

Simultaneous Sample and Hold:
Dual Sample and Hold Matched Channels
Multi Chip Simultaneous Sample and Hold
Capable

Programmable Conversion Modes:
Interrupt-Driven for Shorter Latency
Continuous Modes Optimized for MIPS
Sensitive DSP Solutions

Built-In Internal/System Mid-Scale Error
Calibration

Built-In Mux With 2 Differential or 4
Single-Ended Input Channels

Low Input Capacitance (10 pF Max Fixed,
1 pF Max Switching)

DSP/

P-Compatible Parallel Interface

applications

Portable Digital Radios

Personal Communication Assistants

Cellular

Pager

Scanner

Digitizers

Process Controls

Motor Control

Remote Sensing

Automotive

Servo Controls

Cameras

CSTART

(LSB) D0

D1
D2
D3
D4

BDV

BDGND

D5
D6
D7
D8

(MSB) D9

INT

RD
AP/CH1
AM/CH2
BP/CH3
BM/CH4
AV

VREFP
VREFM
AGND
WR
DGND
DV

CLKIN
CS/OE

DW OR PW PACKAGE

(TOP VIEW)

1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 SEPTEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram

REF

U
X

S/H

4/8/10-Bit

Recyclic

ADC

OSC

(7.5 MHz Min)

Serial/Parallel Conv

and FIFO

3-State

Buffer

Control

Register

Interface

Timing

and

Control

AVDD

DVDD

BDVDD

AGND

DGND

BDGND

AP/CH1

D (09)

CS/OE

INT

CSTART

SysClk

AM/CH2

BP/CH3

BM/CH4

VREFP

VREFM

CLKIN

(15 MHz Max)

VREFMID

S/H

Amplifier

description

The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter
based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million
samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput
as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor
(DSP) or microprocessor (

P) system data bus. D0 through D9 are the digital output terminals with D0 being

the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages
(2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving
feature is further enhanced with a software power-down feature (1

A maximum) and auto power-down (1

maximum) feature.

Many programmable features make this device a flexible general-purpose data converter. The device can be
configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise
immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an
external clock source (CLKIN). Four different modes of conversion are available for different applications. The
interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take
advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers
allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication
applications. Conversion is started by the RD signal, which can also be used for reading data, to maximize the
throughput. Conversion can be started either by the RD or CSTART signal when the device is operating in the
interrupt-driven modes. The dedicated conversion start pin, CSTART, provides a mechanism to simultaneously
sample and convert multiple channels when multiple converters are used in an application.

TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 SEPTEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low
input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal
processing (DSP) companion for mobile communication applications. A switched-capacitor design allows
low-error conversion over the full operating free-air temperature range.

The features that make this device truly a DSP friendly converter include: 1) programmable continuous
conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The
TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation
from 0

C to 70

C. The TLV1562I is characterized for operation over the full industrial temperature range of

C to 85

AVAILABLE OPTIONS

PACKAGED DEVICE

28-TSSOP

(25 MIL PITCH)

(PW)

28-SOIC

(50 MIL PITCH)

(DW)

C to 70

TLV1562CPW

TLV1562CDW

C to 85

TLV1562IPW

TLV1562IDW

TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 SEPTEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with
respect to AGND.

AM/CH2

Differential channel A input minus or single-ended channel 2

AP/CH1

Differential channel A input plus or single-ended channel 1

AVDD

Positive analog supply voltage

BDGND

Digital ground return for the I/O buffers. Unless otherwise noted, all digital interface voltage measurements are with
respect to DGND.

BDVDD

Positive digital supply voltage for I/O buffers

BM/CH4

Differential channel B input minus or single-ended channel 4

BP/CH3

Differential channel B input plus or single-ended channel 3

CLKIN

External clock input. (1 MHz to 15 MHz)

CS/OE

Chip select. A high-to-low transition on this input resets the internal counters and controls and enables the output data
bus D(09) and control inputs (RD, WR) within a maximum setup time. A low-to-high transition disables the output
data bus D(90) and WR within a maximum setup time. This signal also serves as an output enable signal when the
device is programmed into both mono and dual interrupt-driven modes using CSTART as the start of conversion
signal.

CSTART

Conversion start signal. A falling edge starts the sampling period and a rising edge starts the conversion. This signal
acts without CS activated. CSTART connects to DVDD via a 10-k

pull-up resistor if not used.

D(04)

I/O

The lower bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low.

D(59)

913

I/O

The higher bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low. When the host processor writes to the converter, D(9,8) are used as an index to the internal registers.

DGND

Digital ground return for the internal digital logic circuitry

DVDD

Positive digital supply voltage

INT

Interrupt output. The falling edge of INT signals the end of conversion. This output goes from a high impedance state
to low logic level on the fifth falling edge of the system clock and remains low until reset by the rising edge of CS or
RD. INT requires connection of a 10-k

pull-up resistor.

Processor read strobe or synchronous start of conversion/sampling. The falling edge of RD is used to 1) start the
conversion in interrupt-driven mode (if RD is programmed as the start conversion signal); 2) start both conversion
and next sampling plus release of the previous conversion data in both continuous modes. The rising edge of RD
serves as a read strobe and data is 3-stated (approximately 10 ns at 50 pF bus loading) after this edge. Connection
of a 10-k

pull-up resistor is optional.

VREFM

The lower voltage reference value is applied to this terminal.

VREFP

The upper reference voltage value is applied to this terminal. The maximum input voltage range is determined by the
difference between the voltage applied to this terminal and the VREFM terminal.

Processor write strobe. Active low. Connection of a 10-k

pull-up resistor is optional.

detailed description

The TLV1562 analog-to-digital converter is based on an advanced low power recyclic architecture. Two bits of
the conversion result are presented per system clock cycle. A total of 5 system clock (SYSCLK) cycles is
required to complete the conversion. The serial conversion results are converted to a parallel word for output.
The device supports both interrupt-driven (typically found in a SAR type ADC) and continuous (natural for a
pipeline type ADC) modes of conversion. An innovative conversion scheme makes this device perfect for power
sensitive applications with uncompromised speed.

TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 SEPTEMBER 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

control register

The TLV1562 is software configurable. The first two bits, MSBs (D9,8), are used to address the register set. The
rest of the 8 bits are used as data. There are two control registers, CR0 and CR1, for user configuration. All of
these register bits are written to the control register during a write cycle. A description of the control registers
and the input/output data formats are shown in Figure 1.

Pin D9
Index1

Pin D8
Index0

Pin D7

Pin D6

CR0

Offset Calibration Set OMS(1,0)
0,0 = Operate with calibration
0,1 = Measure system offset
1,0 = Measure internal offset
1,1 = Operate without calibration

Input Data Format

Pin D9

Pin D8

Pin D7

Pin D6

Pin D5

Pin D4

Pin D3

Pin D2

Pin D1

Pin D0

Output Data Format

10-Bit Conversion Result

4-Bit Conversion Result

8-Bit Conversion Result

CR1

D(5,4)

= 0,0

OD9

OD3

OD7

CR1

MSB

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

LSB

OD2

OD1

OD0

OD6

OD5

OD4

OD3

OD2

OD1

OD0

MSB

LSB

MSB

LSB

Conversion
Clock Select
0 = Internal
1 = External

Input Type:
0 = Single end
1 = Differential

Conversion Mode Select MS(1,0)
0,0 = Mono interrupt
0,1 = Dual interrupt
1,0 = Mono continuous
1,1 = Dual continuous

Channel Select CS(1,0)
0,0 = Ch1 or pair A
0,1 = Ch2 or pair A
1,0 = Ch3 or pair B
1,1 = Ch4 or pair B

System Offset Calibration: Short the system input to the system AGND
Internal Offset Calibration: Short the two inputs to the S/HA to AGND

Interrupt-Mode
Conversion
Started
0 = By RD
1 = By CSTART

Resolution Select BS(1,0)
0,0 = 10-Bit
0,1 = 4-Bit
1.0 = 8-Bit
1.1 = 12-Bit Test

Output Format
0 = 2's
Complement
1 = Binary

Interrupt-Mode
Auto
Power Down
0 = Disabled
1 = Enabled

SW Power Down
0 = Normal
1 = S/W Power
Down

Register Index

Configuration Register Content

Configuration Result

CR1

D(5,4)

= 0,1

CR1

D(5,4)

= 1,0

Reference delta should be greater than 2 V when swing is reduced.

NOTE:

Z indicates bits write zero read zero back.

Pin D5

Pin D4

Pin D3

Pin D2

Pin D1

Pin D0

Figure 1. Input/Output Data Formats

NOTE:

Channel select bits CR0.(1,0), CS(1,0) are ignored when the device is in the dual (interrupt or
continuous) modes using differential inputs, since both differential input pairs are automatically
selected. CR0.0 (i.e., CS0 bit) is used to determine if channels 1 and 3 or channels 2 and 4 are
selected if single-ended input mode is used.

Part Number TLV1562