TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B DECEMBER 1985 REVISED OCTOBER 1996
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
8-Bit Resolution A/D Converter
D
Microprocessor Peripheral or Stand-Alone
Operation
D
On-Chip 20-Channel Analog Multiplexer
D
Built-in Self-Test Mode
D
Software-Controllable Sample and Hold
D
Total Unadjusted Error . . .
±
0.5 LSB Max
D
Timing and Control Signals Compatible
With 8-Bit TLC540 and 10-Bit TLC1540 A/D
Converter Families
D
CMOS Technology
PARAMETER
TL545
TL546
Channel Acquisition Time
Conversion Time (Max)
Sampling Rate (Max)
Power Dissipation (Max)
1.5
µ
s
9
µ
s
76 x 103
15 mW
2.7
µ
s
17
µ
s
40 x 103
15 mW
description
The TLC545 and TLC546 are CMOS
analog-to-digital converters built around an 8-bit
switched capacitor successive-approximation
analog-to-digital converter. They are designed for
serial interface to a microprocessor or peripheral
via a 3-state output with up to four control inputs
including independent SYSTEM CLOCK, I/O
CLOCK, chip select (CS), and ADDRESS INPUT.
A 4-MHz system clock for the TLC545 and a
2.1-MHz system clock for the TLC546 with a
design that includes simultaneous read/write
operation allowing high-speed data transfers and
sample rates of up to 76,923 samples per second
for the TLC545, and 40,000 samples per second
for the TLC546.
In addition to the high-speed converter and
versatile control logic, there is an on-chip
20-channel analog multiplexer that can be used to
sample any one of 19 inputs or an internal self-test
voltage, and a sample-and-hold that can operate
automatically or under microprocessor control.
The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
switched capacitor design allows low-error (
±
0.5 LSB) conversion in 9
µ
s for the TLC545, and 17
µ
s for the
TLC546, over the full operating temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT A0
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT A8
INPUT A9
INPUT A10
INPUT A11
INPUT A12
GND
V
CC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF +
REF
INPUT A18
INPUT A17
INPUT A16
INPUT A15
INPUT A14
INPUT A13
N PACKAGE
(TOP VIEW)
3 2 1
13 14
5
6
7
8
9
10
11
ADDRESS INPUT
DATA OUT
CS
REF +
REF
INPUT A18
INPUT A17
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT A8
INPUT A9
INPUT A10
4
15 16 17 18
INPUT
A12
GND
INPUT
A13
INPUT
A14
INPUT
A15
INPUT
A16
INPUT
A3
INPUT
A2
INPUT
A1
INPUT
A0
FN PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
INPUT
A1
1
V
SYSTEM CLOCK
I/O CLOCK
CC
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B DECEMBER 1985 REVISED OCTOBER 1996
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TA
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
0
°
C to 70
°
C
TLC545CFN
--
TLC545CN
--
40
°
C to 85
°
C
TLC545IFN
TLC546IFN
TLC545IN
TLC546IN
description (continued)
The TLC545C and the TLC546C are characterized for operation from 0
°
C to 70
°
C. The TLC545I and the
TLC546I are characterized for operation from 40
°
C to 85
°
C.
functional block diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
SYSTEM
CLOCK
CS
I/O
CLOCK
ADDRESS
INPUT
8-Bit
Analog-to-Digital
Converter
(Switched-capacitors)
8
4
2
5
5
8
REF
REF +
DATA
OUT
8-to-1 Data
Selector and
Driver
Control Logic
and I/O
Counters
Output
Data
Register
Input
Multiplexer
Self-Test
Reference
Input
Address
Register
Sample
and
Hold
20-Channel
Analog
Multiplexer
INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
25
26
23
27
22
21
24
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B DECEMBER 1985 REVISED OCTOBER 1996
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 k
TYP
Ci = 60 pF TYP
(equivalent input
capacitance)
5 M
TYP
INPUT
A0 A18
INPUT
A0 A18
operating sequence
Access
Cycle B
(see Note C)
B0
B2
C4
twH(CS)
Don't Care
B7
B0
B1
B2
B3
B4
B5
B6
B7
C3
C2
C1
C0
LSB
MSB
Conversion Data B
MSB
MSB
LSB
Hi-Z State
Don't Care
MSB
LSB
(see Note B)
MSB
Previous Conversion Data A
A7
A7
A6
A5
A4
A3
A2
A1
A0
LSB
B1
B3
MSB
B4
Don't
1
1
See Note A
tconv
Sample Cycle B
8
8
7
6
5
4
3
2
7
6
5
4
3
2
I / O
CLOCK
CS
DATA
OUT
ADDRESS
INPUT
Care
Access
Cycle C
Sample
Cycle C
Hi-Z
State
NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK
after CS
for the channel
whose address exists in memory at that time.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6A0) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the
minimum chip-select setup time has elapsed.
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B DECEMBER 1985 REVISED OCTOBER 1996
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(any input)
0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current range (any input)
±
10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs)
±
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLC545C, TLC546C
0
°
C to 70
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . .
TLC545I, TLC546I
40
°
C to 85
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, T
C
: FN package
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package
260
°
C
. . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B DECEMBER 1985 REVISED OCTOBER 1996
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
recommended operating conditions
TLC545
TLC546
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.75
5
5.5
4.75
5
5.5
V
Positive reference voltage, Vref+ (see Note 2)
0
VCC VCC +0.1
0
VCC VCC +0.1
V
Negative reference voltage, Vref (see Note 3)
0.1
0
VCC
0.1
0
VCC
V
Differential reference voltage, Vref+ Vref (see Note 3)
0
VCC VCC +0.2
0
VCC VCC +0.2
V
Analog input voltage (see Note 3)
0
VCC
0
VCC
V
High-level control input voltage, VIH
2
2
V
Low-level control input voltage, VIL
0.8
0.8
V
Setup time, address bits at data input before I/O CLOCK
,
tsu(A)
200
400
ns
Address hold time, th
0
0
ns
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 2)
3
3
System
clock
cycles
I/O CLOCK frequency, fclock(I/O)
0
2.048
0
1.1
MHz
SYSTEM CLOCK frequency, fclock(SYS)
fclock(I/O)
4
fclock(I/O)
2.1
MHz
Pulse duration, CS high during conversion, twH(CS)
36
36
System
clock
cycles
Pulse duration, SYSTEM CLOCK high, twH(SYS)
110
210
ns
Pulse duration, SYSTEM CLOCK low, twL(SYS)
100
190
ns
Pulse duration, I/O CLOCK high, twH(I/O)
200
404
ns
Pulse duration, I/O CLOCK low, twL(I/O)
200
404
ns
System
fclock(SYS)
1048 kHz
30
30
ns
Clock transition time
System
fclock(SYS) > 1048 kHz
20
20
ns
(see Note 4)
I/O
fclock(I/O)
525 kHz
100
100
ns
I/O
fclock(I/O) > 525 kHz
40
40
ns
Operating free air temperature TA
TLC545C, TLC546C
0
70
0
70
Operating free-air temperature, TA
TLC545I, TLC546I
40
85
40
85
°
C
NOTES:
2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling
edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all "1"s (11111111), while input voltages less than that applied
to REF convert as all "0"s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
to increase.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
µ
s for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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