THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D JUNE 2000 REVISED JANUARY 2001
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
features
D
40-MSPS Sample Rate
D
12-Bit Resolution
D
No Missing Codes
D
On-Chip Sample and Hold
D
77-dB Spurious Free Dynamic Range at
f
IN
= 15.5 MHz
D
5-V Analog and Digital Supply
D
3-V and 5-V CMOS Compatible Digital
Output
D
10.4 Bit ENOB at f
IN
= 31 MHz
D
65 dB SNR at f
IN
= 15.5 MHz
D
120-MHz Bandwidth
D
Internal or External Reference
D
Buffered Differential Analog Input
D
2s Complement Digital Outputs
D
Typical 380 mW Power Consumption
D
Single-Ended or Differential Low-Level
Clock Input
applications
D
Wireless Local Loop
D
Wireless Internet Access
D
Cable Modem Receivers
D
Medical Ultrasound
D
Magnetic Resonant Imaging
description
The THS1240 is a high-speed low noise 12-bit CMOS pipelined analog-to-digital converter. A differential sample
and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog
input. A buffered analog input enables operation with a constant analog input impedance, and prevents transient
voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows
for industrial application with the assurance of no missing codes. The THS1240 can operate with either internal
or external references. Internal reference usage selection is accomplished simply by externally connecting
reference output terminals to reference input terminals.
AVAILABLE OPTIONS
PACKAGE
TA
48-TQFP
(PHP)
40
°
C to 85
°
C
THS1240I
0
°
C to 70
°
C
THS1240C
Copyright
2001, Texas Instruments Incorporated
14 15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
AV
SS
AV
DD
V
IN+
V
IN
AV
DD
V
REFOUT
V
REFIN
V
REFIN
+
V
REFOUT
+
V
BG
AV
SS
AV
DD
17 18 19 20
47 46 45 44 43
48
42
V
AV
CLK+
40 39 38
41
21 22 23 24
37
13
CLK
48 PHP PACKAGE
(TOP VIEW)
CM
DD
DV
DD
DV
SS
DV
SS
DV
DD
DV
SS
DV
DD
DR
V
SS
DR
V
DD
AV
SS
AV
SS
AV
DD
AV
SS
DR
V
SS
AV
SS
DR
V
SS
AV
DD
DR
V
DD
DR
V
DD
DV
SS
AV
SS
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D JUNE 2000 REVISED JANUARY 2001
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
Digital Error Correction
S/H
Stage 1
Stage 10
Reference
3.0 V
2.0 V
AVDD/2
Timing
VIN
VREFOUT+
VCM
CLK+
DVSS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AVDD DVDD
D/A
A/D
D/A
A/D
A/D
VREFOUT
VREFIN+
VREFIN
CLK
1
2
1
Buffer
DRVDD
AVSS
DRVSS
Stages 2 9
VIN+
Stage 11
D10
D11
1 k
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD
2, 5, 12, 43,
45, 47
I
Analog power supply
AVSS
1, 11, 13, 41,
42, 44, 46
I
Analog ground return for internal analog circuitry
CLK+
15
I
Clock input
CLK
16
I
Complementary clock input
D11D0
2536
O
Digital data output bits; LSB= D0, MSB = D11 (2s complement output format)
DRVDD
24, 37, 38
I
Digital output driver supply
DRVSS
23, 39, 40
I
Digital output driver ground return
DVDD
17, 20, 22
I
Positive digital supply
DVSS
18, 19, 21
I
Digital ground return
VBG
10
O
Band gap reference. Bypass to ground with a 1-
µ
F and a 0.01-
µ
F chip capacitor.
VCM
48
O
Common mode voltage output. Bypass to ground with a 0.1-
µ
F and a 0.01-
µ
F chip capacitor.
VIN+
3
I
Analog signal input
VIN
4
I
Complementary analog signal input
VREFIN
7
I
External reference input low
VREFIN+
8
I
External reference input high
VREFOUT+
9
O
Internal reference output. Compensate with a 1-
µ
F and a 0.01-
µ
F chip capacitor.
VREFOUT
6
O
Internal reference output. Compensate with a 1-
µ
F and a 0.01-
µ
F chip capacitor.
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D JUNE 2000 REVISED JANUARY 2001
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional description
The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 1-k
resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs
the final 12 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
DD
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DV
DD
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRV
DD
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AV
SS
and DV
SS
and DRV
SS
0.3 V to 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between DRV
DD
and DV
DD
0.5 V to 5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AV
DD
and DV
DD
0.5 V to 5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital data output
0.3 V to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK peak input current, I
p(CLK)
20
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs), I
p
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: THS1240C 0
°
C to 70
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1240I
40
°
C to 85
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
Sample rate
1
40
MSPS
Analog supply voltage, AVDD
4.75
5
5.25
V
Digital supply voltage, DVDD
4.75
5
5.25
V
Digital output driver supply voltage, DRVDD
3
3.3
5.25
V
CLK + high level input voltage, VIH
3.5
5
5.25
V
CLK + low-level input voltage, VIL
0
1.5
V
CLK pulse-width high, tp(H)
10
12.5
ns
CLK pulse-width low, tp(L)
10
12.5
ns
Operating free air temperature range TA
THS1240C
0
70
°
C
Operating free-air temperature range, TA
THS1240I
40
85
°
C
CLK Input tied to ground with 0.01
µ
F capacitor for single-ended clock source.
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D JUNE 2000 REVISED JANUARY 2001
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DV
DD
= 5 V, DRV
DD
= 3.3 V, internal references, CLK = 40 MHz, single-ended clock source
at 40 MHz with 50% duty cycle (unless otherwise noted)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DNL
Differential nonlinearity
fIN = 15.5 MHz
1
±
0.6
1.25
LSB
No missing codes
Assured
INL
Integral nonlinearity
fIN = 15.5 MHz
±
2
LSB
EO
Offset error
V(VIN+) = V(VIN_) = VCM
14
70
mV
EG
Gain error
7
10
%FSR
All typical values are at TA = 25
°
C.
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I(AVDD)
Analog supply current
V(VIN) = (VCM)
73
110
mA
I(DVDD)
Digital supply current
V(VIN) = (VCM)
2
4
mA
I(DRVDD) Output driver supply current
V(VIN) = (VCM)
2
7
mA
PD
Power dissipation
V(VIN) = (VCM)
380
mW
All typical values are at TA = 25
°
C.
15 pF load on digital outputs
reference
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREFOUT
Negative reference output voltage
1.9
2
2.1
V
VREFOUT+
Positive reference output voltage
2.9
3
3.1
V
VREFIN
External reference supplied
2
V
VREFIN+
External reference supplied
3
V
V(VCM)
Common mode output voltage
AVDD/2
V
I(VCM)
Common mode output current
80
µ
A
All typical values are at TA = 25
°
C.
analog input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RI
Differential input resistance
1
k
CI
Differential input capacitance
4
pF
VI
Analog input common mode range
VCM
±
0.05
V
VID
Differential input voltage range
2
Vp-p
BW
Analog input bandwidth (large signal)
3 dB
120
MHz
All typical values are at TA = 25
°
C.
digital outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = 50
µ
A
0.8DRVDD
V
VOL
Low-level output voltage
IOL = 50
µ
A
0.2DRVDD
VDD
CL
Output load capacitance
15
pF
All typical values are at TA = 25
°
C.
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D JUNE 2000 REVISED JANUARY 2001
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
ac specifications over recommended operating free-air temperature range, AV
DD
= DV
DD
= 5 V,
DRV
DD
= 3.3 V, internal references, CLK = 40 MHz, analog input at 2 dBFS, single-ended clock
source at 40 MHz with 50% duty cycle (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 2.2 MHz
64.6
fIN = 15.5 MHz
64
SNR
Signal-to-noise ratio
fIN = 15.5 MHz, V(IN) = 0.5 dBFS
63
65.5
dB
fIN = 31 MHz
64
fIN = 70 MHz
64
fIN = 2.2 MHz
63.3
fIN = 15.5 MHz
64
SINAD
Signal-to-noise and distortion
fIN = 15.5 MHz, V(IN) = 0.5 dBFS
62
64.5
dB
fIN = 31 MHz
63.2
fIN = 70 MHz
55.7
ENOB
Effective number of bits
fIN = 15.5 MHz
10.2
bits
ENOB
Effective number of bits
fIN = 15.5 MHz, V(IN) = 0.5 dBFS
10
10.4
bits
THD
Total harmonic distortion
fIN = 15.5 MHz
72
68
dBc
THD
Total harmonic distortion
fIN = 15.5 MHz, V(IN) = 0.5 dBFS
71
dBc
fIN = 2.2 MHz
73
fIN = 15.5 MHz
70
77
SFDR
Spurious-free dynamic range
fIN = 15.5 MHz, V(IN) = 0.5 dBFS
72
dBc
fIN = 31 MHz
77
fIN = 70 MHz
59.6
d
fIN = 2.2 MHz
82
2nd Harmonic
Distortion
fIN = 15.5 MHz
87
70
dBc
2nd Harmonic
Distortion
fIN = 31 MHz
77
dBc
fIN = 70 MHz
60.5
d
fIN = 2.2 MHz
73
3rd Harmonic
Distortion
fIN = 15.5 MHz
80.4
70
dBc
3rd Harmonic
Distortion
fIN = 31 MHz
77
dBc
fIN = 70 MHz
60
Two tone SFDR
F1 = 14.9 MHz,
F2 = 15.6 MHz,
Analog inputs at 8 dBFS each
72
dBc
All typical values are at TA = 25
°
C.
operating characteristics over recommended operating conditions, AV
DD
= DV
DD
= 5 V,
DRV
DD
= 3.3 V
switching specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Aperture delay, td(A)
120
ps
Aperture jitter
1
ps RMS
Output delay td(O), after falling edge of CLK+
Digital outputs driving a 15 pF load each
13
ns
Pipeline delay td(PIPE)
6.5
CLK
Cycle
All typical values are at TA = 25
°
C.
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