SN54HC161, SN74HC161

4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-

A Max I

Typical t

= 14 ns

4-mA Output Drive at 5 V

Low Input Current of 1

A Max

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

SN54HC161 . . . J OR W PACKAGE

SN74HC161 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

1 20 19

9 10 11 12 13

NC
Q

A
B

C
D

SN54HC161 . . . FK PACKAGE

(TOP VIEW)

CLK

CLR

LOAD

ENT

RCO

ENP

GND

CLR

CLK

A
B

C
D

ENP

GND

RCO
Q

ENT
LOAD

NC - No internal connection

description/ordering information

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The 'HC161 devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

ORDERING INFORMATION

PACKAGE

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP - N

Tube of 25

SN74HC161N

Tube of 40

SN74HC161D

SOIC - D

Reel of 2500

SN74HC161DR

HC161

-40

C to 85

SOIC - D

Reel of 250

SN74HC161DT

HC161

-40

C to 85

SOP - NS

Reel of 2000

SN74HC161NSR

HC161

Tube of 90

SN74HC161PW

TSSOP - PW

Reel of 2000

SN74HC161PWR

HC161

TSSOP - PW

Reel of 250

SN74HC161PWT

HC161

CDIP - J

Tube of 25

SNJ54HC161J

-55

C to 125

CFP - W

Tube of 150

SNJ54HC161W

-55 C to 125 C

LCCC - FK

Tube of 55

SNJ54HC161FK

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL PRF 38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54HC161, SN74HC161

4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description/ordering information (continued)

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the 'HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q

high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.

SN54HC161, SN74HC161

4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

logic diagram (positive logic)

CLR

LOAD

ENT

ENP

CLK

RCO

For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

Pin numbers shown are for the D, J, N, NS, PW, and W packages.

M1
G2

G4
3D
4R

1, 2T/1C3

M1
G2

G4
3D
4R

1, 2T/1C3

M1
G2

G4
3D
4R

1, 2T/1C3

M1
G2

G4
3D
4R

1, 2T/1C3

Part Number SN74HC161