SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E MARCH 2002 REVISED DECEMBER 2002
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Sub 1-V Operable
D
Max t
pd
of 2 ns at 1.8 V
D
Low Power Consumption, 20-
µ
A Max I
CC
D
±
8-mA Output Drive at 1.8 V
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver is operational at 0.8-V to 2.7-V V
CC
,
but is designed specifically for 1.65-V to 1.95-V
V
CC
operation.
The SN74AUC16245 is designed for
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP DGG
Tape and reel
SN74AUC16245DGGR
AUC16245
40
°
C to 85
°
C
TVSOP DGV
Tape and reel
SN74AUC16245DGVR
MH245
VFBGA GQL
Tape and reel
SN74AUC16245GQLR
MH245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E MARCH 2002 REVISED DECEMBER 2002
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCC
VCC
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCC
VCC
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
NC No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Pin numbers shown are for the DGG and DGV packages.
GQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
K
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E MARCH 2002 REVISED DECEMBER 2002
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
±
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DGG package
70
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package
42
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
0.8
2.7
V
VCC = 0.8 V
VCC
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
0.65
×
VCC
V
VCC = 2.3 V to 2.7 V
1.7
VCC = 0.8 V
0
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
0.35
×
VCC
V
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
3.6
V
VO
Output voltage
Active state
0
VCC
V
VO
Output voltage
3-state
0
3.6
V
VCC = 0.8 V
0.7
VCC = 1.1 V
3
IOH
High-level output current
VCC = 1.4 V
5
mA
VCC = 1.65 V
8
VCC = 2.3 V
9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
IOL
Low-level output current
VCC = 1.4 V
5
mA
VCC = 1.65 V
8
VCC = 2.3 V
9
t/
v
Input transition rise or fall rate
5
ns/V
TA
Operating free-air temperature
40
85
°
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E MARCH 2002 REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = 100
µ
A
0.8 V to 2.7 V
VCC0.1
IOH = 0.7 mA
0.8 V
0.55
VOH
IOH = 3 mA
1.1 V
0.8
V
VOH
IOH = 5 mA
1.4 V
1
V
IOH = 8 mA
1.65 V
1.2
IOH = 9 mA
2.3 V
1.8
IOL = 100
µ
A
0.8 V to 2.7 V
0.2
IOL = 0.7 mA
0.8 V
0.25
VOL
IOL = 3 mA
1.1 V
0.3
V
VOL
IOL = 5 mA
1.4 V
0.4
V
IOL = 8 mA
1.65 V
0.45
IOL = 9 mA
2.3 V
0.6
II
All inputs
VI = VCC or GND
0 to 2.7 V
±
5
µ
A
Ioff
VI or VO = 2.7 V
0
±
10
µ
A
IOZ
VO = VCC or GND
2.7 V
±
10
µ
A
ICC
VI = VCC or GND,
IO = 0
0.8 V to 2.7 V
20
µ
A
Ci
VI = VCC or GND
2.5 V
3
pF
Cio
VO = VCC or GND
2.5 V
7
pF
All typical values are at TA = 25
°
C.
For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
±
0.1 V
VCC = 1.5 V
±
0.1 V
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tpd
A or B
B or A
5.6
0.5
3.1
0.5
2
0.5
1.5
2
0.4
1.9
ns
ten
OE
A or B
10
0.7
4.6
0.7
3.1
0.7
2.1
3.1
0.7
2.6
ns
tdis
OE
A or B
12.8
0.8
6.8
0.8
5
0.8
3.4
4.8
0.5
2.9
ns
operating characteristics, T
A
= 25
°
C
PARAMETER
TEST
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
UNIT
PARAMETER
CONDITIONS
TYP
TYP
TYP
TYP
TYP
UNIT
Cpd
Power
dissipation
Outputs
enabled
f = 10 MHz
22
23
24
25
29
pF
Cpd
dissipation
capacitance
Outputs
disabled
f = 10 MHz
1
1
1
1
1
pF
SN74AUC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES392E MARCH 2002 REVISED DECEMBER 2002
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC/2
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
Open
GND
RL
RL
Data Input
Timing Input
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, slew rate
1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
0.8 V
1.2 V
±
0.1 V
1.5 V
±
0.1 V
1.8 V
±
0.15 V
2.5 V
±
0.2 V
2 k
2 k
2 k
1 k
500
VCC
RL
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
V
CL
15 pF
15 pF
15 pF
30 pF
30 pF
Figure 1. Load Circuit and Voltage Waveforms
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