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FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
·
Latch-Up Performance Exceeds 250 mA Per
JESD 17
·
Member of the Texas Instruments Widebus+TM
Family
·
ESD Protection Exceeds JESD 22
·
Bus Hold on Data Inputs Eliminates the Need
2000-V Human-Body Model (A114-A)
for External Pullup/Pulldown Resistors
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type
latch designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address
bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication
between the A and B data bus, and the address signals are latched and buffered on the Q bus. The
control-function implementation minimizes external timing requirements.
This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one
16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus
to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable
(TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated.
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to V
CC
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of
the drivers.
The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state
of DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LFBGA - GKE
SN74ALVCH32973KR
-40
°
C to 85
°
C
Tape and reel
ACH973
LFBGA - ZKE (Pb-free)
74ALVCH32973ZKER
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 20032004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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rt
GKE OR ZKE PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
P
N
M
L
K
T
R
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
rt
rt
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
1A1
D1
1TOE
1DIR
1B1
1Q1
B
1A2
Y1
GND
GND
1B2
1Q2
C
1A3
D2
V
CC
V
CC
1B3
1Q3
D
1A4
Y2
GND
GND
1B4
1Q4
E
1A5
D3
GND
GND
1B5
1Q5
F
1A6
Y3
V
CC
V
CC
1B6
1Q6
G
1A7
D4
GND
GND
1B7
1Q7
H
1A8
Y4
1LE
1LOE
1B8
1Q8
J
2A1
D5
2TOE
2DIR
2B1
2Q1
K
2A2
Y5
GND
GND
2B2
2Q2
L
2A3
D6
V
CC
V
CC
2B3
2Q3
M
2A4
Y6
GND
GND
2B4
2Q4
N
2A5
D7
GND
GND
2B5
2Q5
P
2A6
Y7
V
CC
V
CC
2B6
2Q6
R
2A7
D8
GND
GND
2B7
2Q7
T
2A8
Y8
2LE
2LOE
2B8
2Q8
FUNCTION TABLES
INPUTS
OPERATION
TOE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
A bus and B bus isolation
INPUTS
OUTPUT
Q
LOE
LE
A
L
H
H
H
L
H
L
L
L
L
X
Q
0
H
X
X
Z
INPUT
OUTPUT
D
Y
L
L
H
H
2
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1LOE
1DIR
To Seven Other Channels
1Q1
C1
1D
1LE
1A1
1B1
1TOE
A4
H4
H3
A1
A3
A6
A5
One of Eight Channels
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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2LOE
2DIR
To Seven Other Channels
2Q1
C1
1D
2LE
2A1
2B1
2TOE
J4
T4
T3
J1
J3
J6
J5
D1
A2
B2
Y1
One of Eight Channels
One of Eight Channels
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
4
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
-0.5
4.6
V
Except I/O and D input ports
(2)
-0.5
4.6
V
I
Input voltage range
V
I/O and D input ports
(2) (3)
-0.5
V
CC
+ 0.5
V
O
Output voltage range
(2) (3)
-0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
-50
mA
I
OK
Output clamp current
V
O
< 0
-50
mA
I
O
Continuous output current
±
50
mA
Continuous current through each V
CC
or GND
±
100
mA
JA
Package thermal impedance
(4)
GKE/ZKE package
40
°
C/W
T
stg
Storage temperature range
-65
150
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
This value is limited to 4.6 V maximum.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
V
CC
Supply voltage
1.65
3.6
V
V
CC
= 1.65 V to 1.95 V
0.65
×
V
CC
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V
1.7
V
V
CC
= 3 V to 3.6 V
2
V
CC
= 1.65 V to 1.95 V
0.35
×
V
CC
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V
0.7
V
V
CC
= 3 V to 3.6 V
0.8
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
V
CC
= 1.65 V
-4
V
CC
= 2.3 V
-12
I
OH
High-level output current
mA
V
CC
= 2.7 V
-12
V
CC
= 3 V
-24
V
CC
= 1.65 V
4
V
CC
= 2.3 V
12
I
OL
Low-level output current
mA
V
CC
= 2.7 V
12
V
CC
= 3 V
24
t/
v
Input transition rise or fall rate
10
ns/V
T
A
Operating free-air temperature
-40
85
°
C
(1)
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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ELECTRICAL CHARACTERISTICS
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
(1)
MAX
UNIT
I
OH
= -100
µ
A
1.65 V to 3.6 V
V
CC
- 0.2
I
OH
= -4 mA
1.65 V
1.2
I
OH
= -6 mA
2.3 V
2
V
OH
2.3 V
1.7
V
I
OH
= -12 mA
2.7 V
2.2
3 V
2.4
I
OH
= -24 mA
3 V
2
I
OL
= 100
µ
A
1.65 V to 3.6 V
0.2
I
OL
= 4 mA
1.65 V
0.45
I
OL
= 6 mA
2.3 V
0.4
V
OL
V
2.3 V
0.7
I
OL
= 12 mA
2.7 V
0.4
I
OL
= 24 mA
3 V
0.55
I
I
V
I
= V
CC
or GND
3.6 V
±
5
µ
A
V
I
= 0.57 V
1.65 V
25
I
BHL
(2)
V
I
= 0.7 V
2.3 V
45
µ
A
V
I
= 0.8 V
3 V
75
V
I
= 1.07 V
1.65 V
-25
I
BHH
(3)
V
I
= 1.7 V
2.3 V
-45
µ
A
V
I
= 2 V
3 V
-75
1.95 V
200
I
BHLO
(4)
V
I
= 0 to V
CC
2.7 V
300
µ
A
3.6 V
500
1.95 V
-200
I
BHHO
(5)
V
I
= 0 to V
CC
2.7 V
-300
µ
A
3.6 V
-500
I
OZ
(6)
V
O
= V
CC
or GND
3.6 V
±
10
µ
A
I
CC
V
I
= V
CC
or GND,
I
O
= 0
3.6 V
60
µ
A
I
CC
One input at V
CC
- 0.6 V,
Other inputs at V
CC
or GND
3 V to 3.6 V
750
µ
A
Control inputs
3
C
i
V
I
= V
CC
or GND
3.3 V
pF
D
4
A ports
4.5
C
io
V
O
= V
CC
or GND
3.3 V
pF
B ports
4.5
C
o
Q
V
O
= V
CC
or GND
3.3 V
3
pF
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25
°
C.
(2)
The bus-hold circuit can sink at least the minimum low sustaining current at V
IL
max. I
BHL
should be measured after lowering V
IN
to GND
and then raising it to V
IL
max.
(3)
The bus-hold circuit can source at least the minimum high sustaining current at V
IH
min. I
BHH
should be measured after raising V
IN
to V
CC
and then lowering it to V
IH
min.
(4)
An external driver must source at least I
BHLO
to switch this node from low to high.
(5)
An external driver must sink at least I
BHHO
to switch this node from high to low.
(6)
For I/O ports, the parameter I
OZ
includes the input leakage current.
6
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
±
0.2 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
w
Pulse duration, LE high
2
2
2
ns
t
su
Setup time, data before LE
0.9
0.9
0.9
ns
t
h
Hold time, data after LE
0.9
0.9
0.9
ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
FROM
TO
±
0.2 V
±
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
D
Y
2.2
0.5
3.2
0.5
3
A
2.2
0.5
3.2
0.5
3
t
pd
Q
ns
LE
2.8
0.5
3.3
0.5
3
A or B
B or A
2.2
0.5
3.2
0.5
3
LOE
Q
2.9
0.7
4.9
0.7
4.7
t
en
TOE
3
0.7
4.6
0.7
4.4
ns
A or B
DIR
3.4
0.7
4.9
0.7
4.7
LOE
Q
2.8
0.5
4.3
0.5
4.1
t
dis
TOE
3.2
0.5
4.3
0.5
4.1
ns
A or B
DIR
3.4
0.5
4.9
0.5
4.7
7
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OPERATING CHARACTERISTICS
(1)
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
T
A
= 25
°
C
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
One f
A
= 10 MHz,
One f
B
= 10 MHz,
A outputs enabled,
TOE = GND,
Q outputs disabled,
12
14
19
LOE = V
CC
,
one A output switching
DIR = GND,
C
L
= 0 pF
One f
A
= 10 MHz,
One f
B
= 10 MHz,
B outputs enabled,
TOE = GND,
Q outputs disabled,
12
14
21
LOE = V
CC
,
one B output switching
DIR = GND,
C
pd
(2)
Power dissipation
C
L
= 0 pF
pF
(each output)
capacitance
One f
A
= 10 MHz,
One f
LE
= 20 MHz,
Q outputs enabled,
One f
Q
= 10 MHz,
A and B I/Os isolated,
11
13
19
TOE = V
CC
,
one Q output switching
LOE = GND,
C
L
= 0 pF
One f
D
= 10 MHz,
One Y output switching,
One f
Y
= 10 MHz,
A and B I/Os isolated,
TOE = V
CC
,
7
8
12
Q outputs disabled
LOE = V
CC
,
C
L
= 0 pF
One f
A
= 10 MHz,
A and B I/Os isolated,
One f
LE
= 20 MHz,
C
pd
Power dissipation
Q outputs disabled,
f
Q
not switching,
4
5
11
pF
(Z)
capacitance
one LE and one A data
TOE = V
CC
,
input switching
LOE = V
CC
,
C
L
= 0 pF
f
A
not switching,
One f
LE
= 20 MHz,
A and B I/Os isolated,
C
pd
(3)
Power dissipation
f
Q
not switching,
Q outputs disabled,
6
7
9
pF
(each LE)
capacitance
TOE = V
CC
,
one LE input switching
LOE = V
CC
,
C
L
= 0 pF
(1)
Total device C
pd
for multiple (m) outputs switching and (n) LE inputs switching = [m * C
pd
(each output)] + [n * C
pd
(each LE)]
(2)
C
pd
(each output) is the C
pd
for each data bit (input and output circuitry) when it operates at 10 MHz (Note: The LE is operating at
20 MHz in this test, but its I
CC
component has been subtracted).
(3)
C
pd
(each LE) is the C
pd
for the clock circuitry only when it operates at 20 MHz.
8
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PARAMETER MEASUREMENT INFORMATION
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
Open
GND
R
L
R
L
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
V
OL
+ V
V
OH
- V
0 V
V
I
0 V
0 V
t
w
V
I
V
I
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
V
LOAD
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
0 V
V
I
V
M
t
PHL
V
M
V
M
V
I
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
M
V
M
t
PLH
V
LOAD
V
LOAD
/2
1.8 V
2.5 V
±
0.2 V
3.3 V
±
0.3 V
1 k
500
500
V
CC
R
L
2
×
V
CC
2
×
V
CC
6 V
V
LOAD
C
L
30 pF
30 pF
50 pF
0.15 V
0.15 V
0.3 V
V
V
CC
V
CC
2.7 V
V
I
V
CC
/2
V
CC
/2
1.5 V
V
M
t
r
/t
f
2 ns
2 ns
2.5 ns
INPUT
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C APRIL 2003 REVISED SEPTEMBER 2004
Figure 1. Load Circuit and Voltage Waveforms
9
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74ALVCH32973ZKER
ACTIVE
LFBGA
ZKE
96
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-250C-168 HR
SN74ALVCH32973KR
ACTIVE
LFBGA
GKE
96
1000
TBD
SNPB
Level-3-220C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
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amplifier.ti.com
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interface.ti.com
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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power.ti.com
Optical Networking
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