PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

SINGLE-ENDED ANALOG-INPUT

24-BIT, 96-kHz STEREO A/D CONVERTER

www.ti.com

FEATURES

24-Bit Delta-Sigma Stereo A/D Converter

Single-Ended Voltage Input: 3 V p-p

Antialiasing Filter Included

Oversampling Decimation Filter

 Oversampling Frequency:

64,

128

 Passband Ripple:

0.05 dB

Stopband Attenuation: 65 dB
On-Chip HPF (Low Cut Filter): 0.84 Hz

(44.1 kHz)

High Performance

THD+N: 96 dB (Typical)
SNR: 105 dB (Typical)
Dynamic Range: 105 dB (Typical)

PCM Audio Interface

Master/Slave Mode Selectable
Data Formats: 24-Bit Left-Justified;

24-Bit I

S; 20-, 24-Bit Right-Justified

Sampling Rate: 16 kHz to 96 kHz

System Clock: 256 f

, 384 f

, 512 f

, 768 f

Dual Power Supplies: 5 V for Analog, 3.3 V for
Digital

Package: 20-Pin SSOP

Lead-Free Product

APPLICATIONS

AV Amp Receiver

MD Player

CD Recorder

Multitrack Receiver

Electric Musical Instrument

DESCRIPTION

The PCM1802 is a high-performance, low-cost,
single-chip stereo analog-to-digital converter with
single-ended analog voltage input. The PCM1802 uses
a delta-sigma modulator with 64- or 128-times over-
sampling, and includes a digital decimation filter and
HPF (low cut filter) which removes the dc component of
the input signal. For various applications, the PCM1802
supports master and slave modes and four data formats
in serial interface. The PCM1802 is suitable for a wide
variety of cost-sensitive consumer applications where
good performance, 5-V analog supply, and 3.3-V digital
supply operation is required. The PCM1802 is
fabricated using a highly advanced CMOS process and
is available in the DB 20-pin SSOP package.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Audio Precision and System Two are trademarks of Audio Precision.
Other trademarks are the property of their respective owners.

2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PACKAGE/ORDERING INFORMATION

PRODUCT

PACKAGE

CODE

OPERATION

TEMPERATURE RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PCM1802DB

20 Lead SSOP

20DB

C to 85

PCM1802

PCM1802DB

Tube

PCM1802DB

20-Lead SSOP

20DB

C to 85

PCM1802

PCM1802DBR

Tape and reel

pin assignments

REF

AGND

PDWN

BYPAS

FSYNC

LRCK

MODE1
MODE0
FMT1
FMT0
OSR
SCKI
V

DGND
DOUT
BCK

PCM1802

(TOP VIEW)

block diagram

Single-End

/Differential

Converter

BCK

VINL

Reference

Single-End

/Differential

Converter

VREF1

VREF2

VINR

5th Order

Delta-Sigma

Modulator

5th Order

Delta-Sigma

Modulator

1/64 (

1/128)

Decimation

Filter

with

DC Cut Filter

Power Supply

AGND

VCC

VDD

DGND

Clock and Timing Control

Serial

Interface

Mode/

Format

Control

LRCK

FSYNC

DOUT

FMT0

FMT1

MODE0

MODE1

BYPAS

OSR

PDWN

SCKI

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

Terminal Functions

TERMINAL

I/O

DESCRIPTIONS

NAME

PIN

I/O

DESCRIPTIONS

AGND

Analog GND

BCK

I/O

Bit clock input/output

BYPAS

HPF bypass control. Low: normal mode (dc cut); High: bypass mode (through)

DGND

Digital GND

DOUT

Audio data output

FMT0

Audio data format select 0. See data format

FMT1

Audio data format select 1. See data format

FSYNC

I/O

Frame synchronous clock input/output

LRCK

I/O

Sampling clock input/output

MODE0

Mode select 0. See interface mode

MODE1

Mode select 1. See interface mode

OSR

Oversampling ratio select. Low:

64 fS; High:

128 fS

PDWN

Power-down control, active low

SCKI

System clock input; 256 fS, 384 fS, 512 fS or 768 fS§

VCC

Analog power supply, 5 V

VDD

Digital power supply, 3.3 V

VINL

Analog input, L-channel

VINR

Analog input, R-channel

VREF1

Reference 1 decoupling capacitor

VREF2

Reference 2 voltage input, normally connected to VCC

Schmitt-trigger input with internal pulldown (50 k

typically), 5-V tolerant

Schmitt-trigger input
§ Schmitt-trigger input, 5-V tolerant

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage:

6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ground voltage differences: AGND, DGND

0.1 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage: FSYNC, LRCK, BCK, DOUT

0.3 V to (V

+ 0.3 V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1

0.3 V to 6.5 V

. . . . . . . . . . . .

Analog input voltage: V

L, V

R, V

REF

1, V

REF

0.3 V to (V

+ 0.3 V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current (any pins except supplies)

10 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ambient temperature under bias

C to 125

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Junction temperature

150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature (soldering)

260

C, 5 s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package temperature (IR reflow, peak)

260

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ś Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

electrical characteristics, all specifications at T

= 25

C, V

= 5 V, V

= 3.3 V, master mode,

= 44.1 kHz, system clock = 384 f

, over sampling ratio =

128, 24-bit data (unless otherwise

noted)

TEST CONDITIONS

PCM1802DB

UNIT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

bits

DATA FORMAT

Audio data interface format

Left justified, I2S,

right justified

Audio data bit length

20, 24

bits

Audio data format

MSB first, 2s complement

Sampling frequency

44.1

kHz

256 fS

4.096

11.2896

24.576

System clock frequency

384 fS

6.144

16.9344

36.864

MHz

System clock frequency

512 fS

8.192

22.5792

49.152

MHz

768 fS

12.288

33.8688

INPUT LOGIC

VIH

See Note 1

VDD

VIL

See Note 1

Input logic level

0.8

VDC

VIH

See Note 2

Input logic level

5.5

VDC

VIL

See Note 2

0.8

IIH

See Note 3

VIN = VDD

IIL

See Note 3

Input logic current

VIN = 0 V

IIH

See Note 4

Input logic current

VIN = VDD

100

IIL

See Note 4

VIN = 0 V

OUTPUT LOGIC

VOH

See Note 5

Output logic level

IOUT = 1 mA

2.8

VDC

VOL

See Note 5

Output logic level

IOUT = 1 mA

0.5

VDC

DC ACCURACY

Gain mismatch channel-to-channel

%FSR

Gain error

%FSR

Bipolar zero error

LCF bypass (see Note 6)

%FSR

NOTES:

1. Pins 911: FSYNC, LRCK, BCK (Schmitt-trigger input, in slave mode)
2. Pins 78, 1520: PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant).
3. Pins 911, 15: FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input).
4. Pins 78, 1620: PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-k

typical pulldown

resistor).

5. Pins 912: FSYNC, LRCK, BCK (in master mode), DOUT
6. Low cut filter

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

electrical characteristics, all specifications at T

= 25

C, V

= 5 V, V

= 3.3 V, master mode,

= 44.1 kHz, system clock = 384 f

, over sampling ratio =

128, 24-bit data (unless otherwise

noted) (continued)

TEST CONDITIONS

PCM1802DB

UNIT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE (see Note 7)

THD+N (V

0 5 dB)

fS = 44.1 kHz

0.0015%

0.003%

THD+N (VIN = 0.5 dB)

fS = 96 kHz (see Note 8)

0.0025%

THD N (V

60 dB)

fS = 44.1 kHz

0.7%

THD+N (VIN = 60 dB)

fS = 96 kHz (see Note 8)

1.2%

Dynamic range

fS = 44.1 kHz, A-weighted

100

105

Dynamic range

fS = 96 kHz, A-weighted (see Note 8)

103

S/N ratio

fS = 44.1 kHz, A-weighted

100

105

S/N ratio

fS = 96 kHz, A-weighted (see Note 8)

103

Channel separation

fS = 44.1 kHz

103

Channel separation

fS = 96 kHz (see Note 8)

ANALOG INPUT

Input voltage

0.6 VCC

Vpp

Center voltage (VREF1)

0.5 VCC

Input impedance

Antialiasing filter frequency response

3 dB

300

kHz

DIGITAL FILTER PERFORMANCE

Passband

0.454 fS

Stopband

0.583 fS

Passband ripple

0.05

Stopband attenuation

Delay time

17.4/fS

HPF frequency response

3 dB

0.019 fS

mHz

POWER SUPPLY REQUIREMENTS

VCC

Voltage range

4.5

5.5

VDC

VDD

Voltage range

2.7

3.3

3.6

VDC

ICC

VCC = 5 V, VDD = 3.3 V

Supply current (see Note 9)

fS = 44.1 kHz VCC = 5 V, VDD = 3.3 V

8.3

IDD

Supply current (see Note 9)

fS = 96 kHz, VCC = 5 V, VDD = 3.3 V (see
Note 8)

fS = 44.1 kHz, VCC = 5 V, VDD = 3.3 V

147

183

Power dissipation; operation

fS = 96 kHz, VCC = 5 V, VDD = 3.3 V (see
Note 8)

176

Power dissipation; power down

VCC = 5 V, VDD = 3.3 V

0.5

TEMPERATURE RANGE

Operation temperature

Thermal resistance (

JA)

20-pin SSOP

115

C/W

NOTES:

7. Analog performance specs are tested with System Two

audio measurement system by Audio Precision

, using 400-Hz HPF,

20-kHz LPF at 44.1-kHz operation, 40-kHz LPF at 96-kHz operation in RMS mode.

8. fS = 96 kHz, system clock = 256 fS, oversampling ratio =

64.

9. Minimum load on DOUT (pin 12), BCK (pin 11), LRCK (pin 10), FSYNC (pin 9).

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER

digital filter--decimation filter frequency response

Figure 1. Overall Characteristics

Frequency [

fS]

200

150

100

50

Oversampling Ratio = x128

Amplitude

AMPLITUDE

FREQUENCY

Figure 2. Overall Characteristics

Frequency [

fS]

200

150

100

50

Amplitude

AMPLITUDE

FREQUENCY

Oversampling Ratio = x64

Figure 3. Stopband Attenuation Characteristics

Frequency [

fS]

100

90

80

70

60

50

40

30

20

10

0.00

0.25

0.50

0.75

1.00

Amplitude

AMPLITUDE

FREQUENCY

Oversampling
Ratio = x128 and x64

Figure 4. Passband Ripple Characteristics

Frequency [

fS]

1.0

0.8

0.6

0.4

0.2

0.0

0.2

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Amplitude

AMPLITUDE

FREQUENCY

Oversampling
Ratio = x128 and x64

All specifications at TA = 25

C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =

128,

24-bit data, unless otherwise noted.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER

HPF (low cut filter) frequency response

Figure 5. LCF Stopband Characteristics

Frequency [

fS/1000]

100

90

80

70

60

50

40

30

20

10

0.0

0.1

0.2

0.3

0.4

Amplitude

AMPLITUDE

FREQUENCY

Figure 6. LCF Passband Characteristics

Frequency [

fS/1000]

1.0

0.8

0.6

0.4

0.2

0.0

0.2

Amplitude

AMPLITUDE

FREQUENCY

analog filter--antialiasing filter frequence response

Figure 7. Antialias Filter Stopband Characteristics

50

45

40

35

30

25

20

15

10

f Frequency Hz

Amplitude

AMPLITUDE

FREQUENCY

100

10k

10M

100k

Figure 8. Antialias Filter Passband Characteristics

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

f Frequency Hz

Amplitude

AMPLITUDE

FREQUENCY

100

100k

10k

All specifications at TA = 25

C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =

128,

24-bit data, unless otherwise noted.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

TYPICAL PERFORMANCE CURVES

Figure 9

0.01

0.02

0.03

0.04

50

25

100

TA Free-Air Temperature 

THD+N

otal Harmonic Distortion + Noise

TOTAL HARMONIC DISTORTION + NOISE

FREE-AIR TEMPERATURE

0.004

0.003

0.002

0.001

Figure 10

100

101

102

103

104

105

106

107

108

109

110

50

25

100

TA Free-Air Temperature 

Dynamic Range and SNR

DYNAMIC RANGE and SNR

FREE-AIR TEMPERATURE

SNR

Dynamic Range

Figure 11

0.01

0.02

0.03

0.04

4.25

4.50

4.75

5.00

5.25

5.50

5.75

VCC Supply Voltage V

THD+N

otal Harmonic Distortion + Noise

TOTAL HARMONIC DISTORTION + NOISE

SUPPLY VOLTAGE

0.004

0.003

0.002

0.001

Figure 12

100

101

102

103

104

105

106

107

108

109

110

4.25

4.50

4.75

5.00

5.25

5.50

5.75

VCC Supply Voltage V

Dynamic Range and SNR

DYNAMIC RANGE and SNR

SUPPLY VOLTAGE

SNR

Dynamic Range

All specifications at TA = 25

C, VCC = 5.0 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =

128,

24-bit data, unless otherwise noted.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

TYPICAL PERFORMANCE CURVES

Figure 13

0.01

0.02

0.03

0.04

fSAMPLE Condition kHz

THD+N

otal Harmonic Distortion + Noise

TOTAL HARMONIC DISTORTION + NOISE

SAMPLE

CONDITION

0.004

0.003

0.002

0.001

44.1

fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio =

128.

fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio =

64.

Figure 14

100

101

102

103

104

105

106

107

108

109

110

Dynamic Range and SNR

DYNAMIC RANGE and SNR

SAMPLE

CONDITION

44.1

SNR

Dynamic Range

fSAMPLE Condition kHz

fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio =

128.

fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio =

64.

output spectrum

Figure 15

f Frequency kHz

140

120

100

80

60

40

20

Input Level = 0.5 dB
Data Points = 8192

Amplitude

AMPLITUDE

FREQUENCY

Figure 16

f Frequency kHz

140

120

100

80

60

40

20

Amplitude

AMPLITUDE

FREQUENCY

Input Level = 60 dB
Data Points = 8192

All specifications at TA = 25

C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =

128,

24-bit data, unless otherwise noted.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

TYPICAL PERFORMANCE CURVES

100 90 80 70 60 50 40 30 20 10

Signal Level dB

THD+N

otal Harmonic Distortion + Noise

TOTAL HARMONIC DISTORTION + NOISE

SIGNAL LEVEL

100

0.1

0.01

0.001

Figure 17

supply current

I CC

and I

Supply Current

SUPPLY CURRENT

SAMPLE

CONDITION

44.1

ICC

fSAMPLE Condition kHz

IDD

fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio =

128.

fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio =

64.

Figure 18

All specifications at TA = +25

C, VCC = 5 V, VDD = 3.3 V, Master Mode, fS = 44.1 kHz, system clock = 384fS, oversampling ratio =

128,

24-bit data, unless otherwise noted.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

PCM1802 consists of a reference circuit, two channels of single-ended-to-differential converter, fifth-order
delta-sigma modulator with full differential architecture, decimation filter with low cut filter, and a serial interface
circuit. Figure 19 illustrates the total architecture of PCM1802, Figure 20 illustrates the architecture of
single-ended-to-differential converter and antialiasing filter, and Figure 21 illustrates the block diagram of
fifth-order delta-sigma modulator and transfer function. An on-chip high-precision reference with one external
capacitor provides all reference voltages that are needed in the PCM1802, and defines the full scale voltage
range for both channels. On-chip single-ended-to-differential signal converters save the design, space, and
extra parts cost for external signal converters. Full differential architecture provides a wide dynamic range and
excellent power supply rejection performance. The input signal is sampled at a

64 or

128 oversampling rate,

thus eliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five
integrators using the switched capacitor technique and a comparator, shapes the quantization noise generated
by the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma modulation
randomizes the modulator outputs and reduces the idle tone level. The 64-f

or 128-f

, 1-bit stream from the

delta-sigma modulator is converted to a 1-f

, 24-bit or 20-bit digital signal by removing high-frequency noise

components with a decimation filter. The dc component of the signal is removed by the LCF, and the LCF output
is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial
formats.

Single-End

/Differential

Converter

BCK

VINL

Reference

Single-End

/Differential

Converter

VREF1

VREF2

VINR

5th Order

Delta-Sigma

Modulator

5th Order

Delta-Sigma

Modulator

1/64 (

1/128)

Decimation

Filter with

DC Cut Filter

Power Supply

AGND

VCC

VDD

DGND

Clock and Timing Control

Serial

Interface

Mode/

Format

Control

LRCK

FSYNC

DOUT

FMT0

FMT1

MODE0

MODE1

BYPAS

OSR

PDWN

SCKI

Figure 19. Block Diagram

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

VINL

VREF1

VREF2

0.1

20 k

Delta-Sigma

Modulator

(+)

()

Reference

VCC

Figure 20. Analog Front End (Left Channel)

1st

SW-CAP

Integrator

Analog
In
X(z)

2nd

SW-CAP

Integrator

3rd

SW-CAP

Integrator

4th

SW-CAP

Integrator

5th

SW-CAP

Integrator

Digital
Out
Y(z)

Comparator

Qn(z)

H(z)

1-Bit
DAC

STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]

Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function

Figure 21. Block Diagram of Fifth-Order Delta-Sigma Modulator

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

system clock

The PCM1802 supports 256 f

, 384 f

, 512 f

, and 768 f

as the system clock, where f

is the audio sampling

frequency. The system clock must be supplied on SCKI (pin 15).

The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating
at 256 f

, 384 f

, 512 f

, or 768 f

in slave mode. In master mode, the system clock frequency must be selected

by MODE0 (pin 19) and MODE1 (pin 20), and 768 f

is not available. For system clock inputs of 384 f

, 512 f

and 768 f

, the system clock is divided to 256 f

automatically, and the 256 f

clock is used to operate the

delta-sigma modulator and the digital filter.

Table 1 shows the relationship of typical sampling frequencies and system clock frequencies, and Figure 22
shows system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING RATE

FREQUENCY

SYSTEM CLOCK FREQUENCY (MHz)

FREQUENCY

(kHz)

256 fS

384 fS

512 fS

768 fS

8.192

12.288

16.384

24.576

44.1

11.2896

16.9344

22.5792

33.8688

12.288

18.432

24.576

36.864

16.384

24.576

32.768

49.152

88.2

22.5792

33.8688

45.1584

24.576

36.864

49.152

SCKI

0.8 V

SCKI

2.0 V

tSCKL

tSCKH

PARAMETER

MIN

MAX

UNIT

tSCKH

System clock pulse width, high

tSCKL

System clock pulse width, low

Figure 22. System Clock Timing

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

power-on reset sequence

The PCM1802 has an internal power-on reset circuit and initialization (reset) is performed automatically when
the power supply (V

) exceeds 2.2 V (typ). While V

< 2.2 V (typ), and for 1024 system-clock counts after

> 2.2 V (typ), the PCM1802 stays in the reset state and the digital output is forced to zero. The digital output

is valid after the reset state is released and the time of 4480/f

has passed. Figure 23 illustrates the internal

power-on reset timing and the digital output for power-on reset.

System Clock

2.6 V
2.2 V
1.8 V

Internal Reset

DOUT

Zero Data

Normal Data

Reset

VDD

Reset Removal

1024 System Clocks

4480 / fS

Figure 23. Internal Power-On Reset Timing

serial audio data interface

The PCM1802 interfaces with the audio system through BCK (pin 11), LRCK (pin 10), FSYNC (pin 9), and DOUT
(pin 12).

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

interface mode

The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1
(pin 20) and MODE0 (pin 19) as shown in Table 2.

In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802
and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data
transfer from an external controller.

Table 2. Interface Mode

MODE1

MODE0

INTERFACE MODE

Slave mode (256 fS, 384 fS, 512 fS, 768 fS)

Master mode (512 fS)

Master mode (384 fS)

Master mode (256 fS)

(1) Master mode
In master mode, BCK, LRCK and FSYNC work as output pins, and these pins are controlled by timing which
is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the
PCM1802. The rising edge of FSYNC indicates the starting point of the converted audio data and the falling
edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2

LRCK.

The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64

LRCK. The 768 f

system clock is not available in master mode.

(2) Slave mode
In slave mode, BCK, LRCK and FSYNC work as input pins. FSYNC is used to enable the BCK signal, and
the PCM1802 can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts either the
64 BCK/LRCK or the 48 BCK/LRCK format. The delay of FSYNC from the LRCK transition must be within
16 BCKs for the 64 BCK/LRCK format and within 12 BCKs for the 48 BCK/LRCK format.

data format

The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1
(pin 18) and FMT0 (pin 17) as shown in Table 3. Figure 24 and Figure 26 illustrate the data formats in slave
mode and master mode, respectively.

Table 3. Data Format

FORMAT#

FMT1

FMT0

FORMAT

Left justified, 24 bit

I2S, 24 bit

Right justified, 24 bit

Right justified, 20 bit

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

interface timing

Figure 25 and Figure 27 illustrate the interface timing in slave mode and master mode, respectively.

FORMAT 0: FMT[1:0] = 00

24-Bit, MSB-First, Left-Justified

BCK

LRCK

Right-Channel

Left-Channel

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 1: FMT[1:0] = 01

24-Bit, MSB-First, IIS

LRCK

Right-Channel

Left-Channel

BCK

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 2: FMT[1:0] = 10

24-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 3: FMT[1:0] = 11

20-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

18 19 20

MSB

LSB

18 19 20

MSB

LSB

FSYNC

Figure 24. Audio Data Format (Slave Mode: FSYNC, LRCK, BCK Work as Inputs)

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

interface timing (continued)

BCK

FSYNC

LRCK

DOUT

t(FSSU)

t(BCKH)

t(BCKL)

t(LRHD)

t(FSHD)

t(LRCP)

t(LRSU)

t(BCKP)

t(CKDO)

t(LRDO)

1.4 V

0.5 VDD

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150

t(BCKH)

BCK pulse duration high

t(BCKL)

BCK pulse duration low

t(LRSU)

LRCK setup time to BCK rising edge

t(LRHD)

LRCK hold time to BCK rising edge

t(LRCP)

LRCK period

t(FSSU)

FSYNC setup time to BCK rising edge

t(FSHD)

FSYNC hold time to BCK rising edge

t(CKDO)

Delay time, BCK falling edge to DOUT valid

t(LRDO)

Delay time, LRCK edge to DOUT valid

Rise time of all signals

Fall time of all signals

NOTE: Timing measurement reference level is (VIH/VIL)/2. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load

capacitance of DOUT is 20 pF.

Figure 25. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, BCK Work as Inputs)

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

interface timing (continued)

FORMAT 0: FMT[1:0] = 00

24-Bit, MSB-First, Left-Justified

BCK

LRCK

Right-Channel

Left-Channel

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 1: FMT[1:0] = 01

24-Bit, MSB-First, IIS

LRCK

Right-Channel

Left-Channel

BCK

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 2: FMT[1:0] = 10

24-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

22 23 24

MSB

LSB

22 23 24

MSB

LSB

FSYNC

FORMAT 3: FMT[1:0] = 11

20-Bit, MSB-First, Right-Justified

LRCK

Right-Channel

Left-Channel

BCK

DOUT

18 19 20

MSB

LSB

18 19 20

MSB

LSB

FSYNC

Figure 26. Audio Data Format (Master Mode: FSYNC, LRCK, BCK Work as Outputs)

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

interface timing (continued)

BCK

FSYNC

LRCK

DOUT

t(CKFS)

t(BCKH)

t(BCKL)

t(CKLR)

t(LRCP)

t(BCKP)

t(CKDO)

t(LRDO)

0.5 VDD

t(FSYP)

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150

1/(64 fS)

1200

t(BCKH)

BCK pulse width high

600

t(BCKL)

BCK pulse width low

600

t(CKLR)

Delay time BCK falling edge to LRCK valid

t(LRCP)

LRCK period

1/ fS

t(CKFS)

Delay time BCK falling edge to FSYNC valid

t(FSYP)

FSYNC period

1/(2 fS)

t(CKDO)

Delay time, BCK falling edge to DOUT valid

t(LRDO)

Delay time, LRCK edge to DOUT valid

Rise time of all signals

Fall time of all signals

NOTE: Timing measurement reference level is (VIH/VIL) / 2. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load

capacitance of all signals is 20 pF.

Figure 27. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, BCK Work as Outputs)

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

synchronization with digital audio system

In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does
not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK
and SCKI.

If the relationship between LRCK and SCKI changes more than

6 BCKs for 64 BCK/frame (

5 BCKs for

48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within
1/f

and digital output is forced into BPZ code until re-synchronization between LRCK and SCKI is completed.

In the case of changes less than

5 BCKs for 64 BCK/frame (

4 BCKs for 48 BCK/frame), resynchronization

does not occur.

Figure 28 illustrates digital output response for loss of synchronization and resynchronization. During undefined
data, some noise might be generated in the audio signal. Also, the transition of normal to undefined data and
undefined or zero data to normal creates a data discontinuity in the digital output, which can generate some
noise in the audio signal.

It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode,
data format, or oversampling control is changed.

1/fS

32/fS

NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

Figure 28. ADC Digital Output for Loss of Synchronization and Resynchronization

power down, LCF bypass, oversampling control

PDWN (pin 7) controls the entire ADC operation. During power-down mode, both the supply current for the
analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized.
Also, DOUT (pin 12) is disabled and no system clock is accepted during power-down mode.

Table 4. Power-Down Control

PDWN

Power-down mode

LOW

Power-down mode

HIGH

Normal operation mode

The built-in function for dc component rejection can be bypassed using the BYPAS (pin 8) control. In bypass
mode, the dc components of the analog input signal, internal dc offset, etc., are also converted and included
in the digital output data.

Table 5. LCF Bypass Control

BYPAS

LCF (low-cut filter) mode

LOW

Normal (no dc component on DOUT) mode

HIGH

Bypass (dc component on DOUT) mode

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

PRINCIPLES OF OPERATION

power down, LCF bypass, oversampling control (continued)

OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator,

64 or

128. The

128 mode is

available for f

< 50 kHz, and must be used carefully as performance is affected by the duty cycle of the 384 f

system clock.

Table 6. Oversampling Control

OSR

Oversampling ratio

LOW

HIGH

128 (fS < 50 kHz)

APPLICATION INFORMATION

typical circuit connection diagram

Figure 29 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about
8 Hz.

VINL

PCM1802

VINR

VREF1

VREF2

VCC

AGND

PDWN

BYPAS

FSYNC

LRCK

MODE1

DGND

MODE0

FMT1

FMT0

OSR

DOUT

BCK

VDD

SCKI

Oversampling

System Clock

L-Ch IN

R-Ch IN

0 V

5 V

C5§

Power Down

LCF Bypass

Control

L/R Clock

Frame Sync.

Audio Data
Processor

Mode [1:0]

Format [1:0]

3.3 V

0 V

Data Clock

Data Out

Control

R1#

C1, C2: A 1-

F capacitor gives 8-Hz (

= 1

20 k

) cutoff frequency for input HPF in normal operation, and requires a power-on settling

time with 20-ms time constant in the power-on initialization period.

C3, C4: Bypass capacitors, 0.1-

F ceramic and 10-

F tantalum, depending on layout and power supply.

§ C5: 0.1-

F ceramic and 4.7-

F tantalum capacitors are recommended.

ś C6: 0.1-

F ceramic and 4.7-

F tantalum capacitors are recommended for using a noise analog power supply. These capacitor are not required

for clean analog supply.

# R1: 1-k

resistor is recommended for using a noisy analog power supply. This resistor is shorted for a clean analog supply.

Figure 29. Typical Circuit Connection

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

APPLICATION INFORMATION

board design and layout considerations

, V

pins

The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground
pins with 0.1-

F ceramic and 10-

F tantalum capacitors as close to the pins as possible to maximize the

dynamic performance of the ADC.

AGND, DGND pins

To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected
internally. These grounds should have very low impedance to avoid digital noise feeding back into the analog
ground. They should be connected directly to each other under the parts to reduce the potential noise problem.

pins

A 1-

F capacitor is recommended as an ac-coupling capacitor which gives 8-Hz cutoff frequency. If a higher

full-scale input voltage is required, it can be accommodated by adding only one series resistor to each V

pin.

REF

1 pin

A 0.1-

F ceramic and 10-

F chemical capacitors are recommended between V

REF

1 and AGND to insure low

source impedance of ADC references. These capacitors should be located as close as possible to the V

REF

pin to reduce the dynamic errors on ADC references.

REF

2 pin

The differential voltage between V

REF

2 and AGND sets the analog input full-scale range. A 0.1-

F ceramic and

10-

F chemical capacitors are recommended between V

REF

2 and AGND with insertion of a 1-k

resistor

between VCC and VREF2 for using a noisy analog power supply. These capacitors and resistor are not required
for clean analog supply. These capacitors should be located as close as possible to the V

REF

2 pin to reduce

the dynamic errors on ADC references. Full-scale input level is affected by this 1-k

resistor and decreases

by 3%.

DOUT pin

The DOUT pin has enough load drive capability, but locating a buffer near the PCM1802 and minimizing load
capacitance is recommended if the DOUT line is long, in order to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.

system clock

The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the
system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time
difference between the system clock transition and the BCK or LRCK transition.

PCM1802

SLES023B DECEMBER 2001 REVISED MARCH 2002

www.ti.com

MECHANICAL DATA

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

4040065 /D 09/00

28 PINS SHOWN

Gage Plane

8,20
7,40

0,15 NOM

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,90

7,90

10,50

9,90

0,38

5,60
5,00

0,22

6,50

0,05 MIN

5,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

0,15

 8

0,10

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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Part Number PCM1802