1
Semiconductor
Features
· HC/HCT354
- Transparent Data and Select Latches
· Buffered Inputs
· Three-State Complementary Outputs
· Bus Line Driving Capability
· Typical Propagation Delay: V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
- Data to Output = 18ns
· Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
· Wide Operating Temperature Range . . . -55
o
C to 125
o
C
· Balanced Propagation Delay and Transition Times
· Significant Power Reduction Compared to LSTTL
Logic ICs
· HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
· HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
µ
A at V
OL
, V
OH
Description
The CD54HC354, CD74HC354, and CD74HCT354 are data
selectors/multiplexers that select one of eight sources. In both
types, the data select bits S0, S1 and S2 are stored in
transparent latches that are enabled by a low latch enable
input, LE.
In the HC/HCT354 the data enable input, E, controls
transparent latches that pass data to the outputs when E is
high and latches in new data when E is low.
In both types the three-state outputs are controlled by three
output-enable inputs OE1, OE2, and OE3.
Pinout
CD54HC354
(CERDIP)
CD74HC354, CD74HCT354
(PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC354F3A
-55 TO 125
20 Ld CERDIP
CD74HC354E
-55 to 125
20 Ld PDIP
CD74HCT354E
-55 to 125
20 Ld PDIP
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D0
D1
E
GND
V
CC
Y
OE3
OE2
Y
OE1
S0
S1
S2
LE
SCHS277D - November 1997 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
CD54HC354, CD74HC354,
CD74HCT354
8-Line to 1-Line Data Selector/Multiplexer/Register
With 3-State Outputs
[ /Title
(CD74
HC354
,
CD74
HCT35
4)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Input
Multip
lexer/
Regis-
2
Functional Diagram
19
18
8
LE
11
6
1
7
5
4
3
2
D0
D1
D2
D3
D4
D5
D6
D7
15
16
17
9
OE1
OE2
OE3
S2
S1
S0
12
13
14
Y
Y
E
TRUTH TABLE
INPUTS
OUTPUTS
SELECT (NOTE 1 )
ENABLE
DATA
OUTPUT ENABLES
S2
S1
S0
E
OE1
OE2
OE3
Y
Y
X
X
X
X
H
X
X
Z
Z
X
X
X
X
X
H
X
Z
Z
X
X
X
X
X
X
L
Z
Z
L
L
L
L
L
L
H
D0
D0
L
L
L
H
L
L
H
D0
n
D0
n
L
L
H
L
L
L
H
D1
D1
L
L
H
H
L
L
H
D1
n
D1
n
L
H
L
L
L
L
H
D2
D2
L
H
L
H
L
L
H
D2
n
D2
n
L
H
H
L
L
L
H
D3
D3
L
H
H
H
L
L
H
D3
n
D3
n
H
L
L
L
L
L
H
D4
D4
H
L
L
H
L
L
H
D4
n
D4
n
H
L
H
L
L
L
H
D5
D5
H
L
H
H
L
L
H
D5
n
D5
n
H
H
L
L
L
L
H
D6
D6
H
H
L
H
L
L
H
D6
n
D6
n
CD54HC354, CD74HC354, CD74HCT354
3
H
H
H
L
L
L
H
D7
D7
H
H
H
H
L
L
H
D7
n
D7
n
H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); X = Don't Care; Z = High Impedance State (Off
State); D0
n
...D7
n
= the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of
data control.
NOTE:
1. This column shows the input address setup with LE low.
TRUTH TABLE (Continued)
INPUTS
OUTPUTS
SELECT (NOTE 1 )
ENABLE
DATA
OUTPUT ENABLES
S2
S1
S0
E
OE1
OE2
OE3
Y
Y
Block Diagram
15
D
A
T
A
R
E
G
I
S
T
E
R
S
1
8
O
F
S
E
L
E
C
T
O
R
ADDRESS
DECODE
A
R
D
D
R
E
S
S
E
G
I
S
T
E
R
16
17
9
8
7
6
5
4
3
2
1
11
14
13
12
OE1
OE2
OE3
E
D0
D1
D2
D3
D4
D5
D6
D7
LE
S0
S1
S2
18
19
Y
Y
BUFFERS
ENABLE LOGIC
CD54HC354, CD74HC354, CD74HCT354
4
Logic Diagram
FIGURE 1. HC/HCT354 LOGIC DIAGRAM
E
15
16
17
OE1
OE2
OE3
P
N
E
E
P
N
1 OF 8 LATCHES
E
P
N
8 (7, 6, 5, 4, 3, 2, 1)
D0
E
E
P
V
CC
N
Y
19
GND
P
V
CC
N
Y
18
TO 7 OTHER
SEL0
LATCHES
E
9
OTHER 7
LATCH OUTPUTS
CONNECT HERE
TO OTHER 7 LATCHES
SEL0
SEL1
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
LE
P
N
LE
LE
P
N
LE
LE
P
N
LE
LE
P
N
LE
LE
P
N
LE
LE
P
N
LE
SL0
SL1
SL2
SL2
SL1
SL0
14
13
12
S2
S1
S0
V
CC
GND
20
10
11
LE
LE
GND
LE
CD54HC354, CD74HC354, CD74HCT354
5
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .±
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
(Bus Driver)
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
(Bus Driver)
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
±
0.1
-
±
1
-
±
1
µ
A
CD54HC354, CD74HC354, CD74HCT354
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