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PRODUCT PREVIEW

FEATURES

APPLICATIONS

DESCRIPTION

CLKP

CLKM

INP

INM

VCMOUT/

REFIN

PLL

14-Bit ADC

REFERENCE

CLKOUT

OVR

IREF

SCLK

SEN

SDA

RESET

D13-D0

IN CMOS MODE

DIGITAL

ENCODER

CONTROL I/F

ADS5545

SLWS180 SEPTEMBER 2005

14-BITS, 170 MSPS ADC WITH LVDS/CMOS OUTPUTS

Wireless Communication

Maximum Sample Rate: 170 MSPS

Software Defined Radio

14-Bit Resolution

Power Amplifier Linearization

No Missing Codes

802.16d/e

Power Dissipation

Test and Measurement Instrumentation

 Core Power: 1 W

High Definition Video

 Total Power: 1.22 W

Medical Imaging

Internal Sample and Hold

Radar Systems

73.5-dBFS SNR at 70-MHz IF

85-dBc SFDR at 70-MHz IF

Parallel CMOS and LVDS Output Options

Internal Reference, External Reference
Support

3.3-V Analog and Digital Supply

48-Pin QFN Package (7 mm

7 mm)

The ADS5545 is a high performance 14-bit 170-MSPS ADC. Using an internal sample and hold and low jitter
clock buffer this ADC supports high SNR and high SFDR at high IF. With programmable options for parallel
CMOS and LVDS outputs, this device is available in a compact 48-pin QFN package. The device provides
internal references or can optionally be driven with an external reference. The device is specified over a 40

C to

C operating range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.

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PRODUCT PREVIEW

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ADS5545

SLWS180 SEPTEMBER 2005

PACKAG/ORDERING INFORMATION

(1)

SPECIFIED

PACKAGE

ORDERING

TRANSPORT

PACKAGE-

PACKAGE

PRODUCT

TEMPERATURE

MARKING

NUMBER

MEDIA,

LEAD

DESIGNATOR

RANGE

QUANTITY

ADS5545

48-QFN

RGZ

C to 85

ADS5545IRGZ

(1)

= TBD,

= TBD

VALUE

UNIT

AVDD

Supply voltage range

0.3 V to 3.9

DRVDD Supply voltage range

0.3 V to 3.9

Voltage between AGND and DRGND

0.3 to 0.3

Voltage between AVDD to DRVDD

0.3 to 3.3

Voltage applied to external pin

0.3 to 2

Voltage applied to analog input pins

0.3 V to minimum (3.6, AVDD + 0.3 V )

Operating free-air temperature range

40 to 85

Operating junction temperature range

125

stg

Storage temperature range

to 150

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

220

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN

NOM

MAX

UNIT

SUPPLIES AND REFERENCES

AVDD

Analog supply voltage

3.3

3.6

DRVDD

Digital supply voltage

3.3

3.6

CLOCK INPUT

Input clock sample rate

170

MSPS

Input clock amplitude, differential

Vpp

Input clock duty cycle

50%

Operating free-air temperature

Typical values at 25

C, min, max values are across the full temperature range T

MIN

= 40

C to T

MAX

= 85

C, AVDD = DRVDD

= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, 1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

Resolution

bits

No missing codes

Assured

DNL

Differential non-linearity

0.9

0.5

TBD

LSB

INL

Integral non-linearity

LSB

Offset error

Offset temperature coefficient

TBD

ppm/

Gain error

%FS

Gain temperature coefficient

TBD

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PRODUCT PREVIEW

ADS5545

SLWS180 SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

Typical values at 25

C, min, max values are across the full temperature range T

MIN

= 40

C to T

MAX

= 85

C, AVDD = DRVDD

= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, 1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

ICC

Total supply current

= TBD

369

IAVDD

Analog supply current

= TBD

315

LVDS mode, F

= TBD, C

= 5 pF

IDRVDD

Digital supply current

CMOS mode, F

= TBD, C

= 5 pF

Total power dissipation

LVDS mode, F

= TBD

1.22

Power down dissipation

Clock running

TBD

REFERENCE VOLTAGES

VREFB

Reference bottom

0.5

VREFT

Reference top

2.5

VCM

Common mode voltage (internal)

1.5

VCM output current

ANALOG INPUT

Differential input capacitance

Analog input common mode range

VCM

0.1

Differential input voltage range

Vpp

Analog input bandwidth

3 dB, source impedance 50

400

MHz

DYNAMIC AC CHARACTERISTICS

= 10 MHz

SFDR

Spurious free dynamic range

= 70 MHz

dBc

= 150 MHz

= 10 MHz

SNR

Signal-to-noise ratio

= 70 MHz

73.5

dBFS

= 150 MHz

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PRODUCT PREVIEW

DIGITAL CHARACTERISTICS

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

= 170 MSPS

= 10.1 MHz

SFDR = 91.5 dBc
SNR = 74.09
dBFS

ADS5545

SLWS180 SEPTEMBER 2005

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, I

= 3.5 mA, R

= 100

(1)

All LVDS and CMOS specifications are characterized, but not tested at production.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

2.4

Low-level input voltage

0.8

High-level input current

Low-level input current

Input capacitance

DIGITAL OUTPUTS CMOS MODE

High-level output voltage

3.3

Low-level output voltage

Output capacitance

Output capacitance inside the device, from either

output to ground

DIGITAL OUTPUTS LVDS MODE

High-level output voltage

1375

Low-level output voltage

1025

Output differential voltage, |V

350

Output offset voltage

(1)

Common-mode voltage of OUTP and OUTM

1200

Output capacitance

Output capacitance inside the device, from either

output to ground

Change in |V

|, |

Change in |V

|, |

(1)

refers to the LVDS buffer current setting, R

is the differential load resistance between the LVDS output pair.

Figure 1. ADS5545 FFT Plot at 170 MSPS and 10-MHz Input

Part Number ADS5545

Document Outline