STPC
®
ELITE
X86 Core General Purpose PC Compatible System - on - Chip
Release 1.3 - January 29, 2002
1/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Logic Diagram
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POWERFUL X86 PROCESSOR
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64-BIT SDRAM CONTROLLER AT 100MHz
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INTEGRATED PCI NORTH / SOUTH
BRIDGE CONTROLLER
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ISA MASTER / SLAVE / DMA
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16-BIT LOCAL BUS INTERFACE FOR LOW
COST AND EMBEDDED APPLICATIONS
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EIDE CONTROLLER
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INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
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POWER MANAGEMENT UNIT
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I²C INTERFACE
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16 ENHANCED GENERAL PURPOSE I/Os.
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JTAG IEEE1149.1
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PROGRAMMABLE OUTPUT CLOCK UP TO
135MHz
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COMMERCIAL AND INDUSTRIAL TEM-
PERATURE RANGES
DESCRIPTION
The STPC Elite integrates a fully static x86
processor up to 133 MHz, fully compatible with
standard x86 processors, and combines it with
powerful chipset to provide a general purpose PC
compatible subsystem on a single device. The
device is packaged in a 388 Ball Grid Array
(PBGA).
The STPC Elite has a low voltage operation with
V
CORE
= 2.5V and has 5V tolerant I/Os (3.3V
output levels).
PBGA388
ST
PC
EL
ITE
x86
Core
Host I/F
SDRAM
CONTROL
PCI
I/F
PCI
ISA
I/F
EIDE
ctrl
PCI
I/F
ISA BUS
EIDE
L.B.
I/F
LOCAL BUS
IPC
JTAG
PMU
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Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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X86 Processor core
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Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
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Can access up to 4GB of external memory.
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8KByte unified instruction and data cache
with write back and write through capability.
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Parallel processing integral floating point unit,
with automatic power down.
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Clock core speeds up to of 100 MHz in x1
clock mode and 133MHz in x2 mode.
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Fully static design for dynamic clock control.
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Low power and system management modes.
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SDRAM Controller
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64-bit data bus.
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Up to 100MHz SDRAM clock speed.
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Supports up to 128 MB system memory.
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Supports 16-, 64- and 128-Mbit memories.
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Supports up to 4 memory banks.
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Supports buffered, non buffered, registered
DIMMs
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4-line write buffers for CPU to DRAM and PCI
to DRAM cycles.
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4-line read prefetch buffers for PCI masters.
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Programmable latency
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Programmable timing for DRAM parameters.
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Supports -8, -10, -12, -13, -15 memory parts
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Supports memory hole between 1MB and
8MB for PCI/ISA busses.
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PCI Controller
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Compliant with PCI 2.1 specification.
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Integrated PCI arbitration interface. Up to 3
masters can connect directly. External logic
allows for greater than 3 masters.
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Translation of PCI cycles to ISA bus.
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Translation of ISA master initiated cycle to
PCI.
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Support for burst read/write from PCI master.
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0.25X, 0.33X and 0.5X Host clock PCI clock.
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ISA master/slave
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Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock
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Supports programmable extra wait state for
ISA cycles
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Supports I/O recovery time for back to back
I/O cycles.
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Fast Gate A20 and Fast reset.
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Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
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Supports flash ROM.
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Supports ISA hidden refresh.
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Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host
bus. NSP compliant.
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16-bit I/O decoding.
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Local Bus interface
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Multiplexed with ISA/DMA/Timer functions.
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High speed, low latency bus.
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Supports 32-bit Flash burst.
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16-bit data bus with word steering capability.
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Separate memory and I/O address spaces.
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Programmable timing (Host clock granularity)
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Supports 2 cachable banks of 16MB flash
devices with boot block shadowed to
0x000F0000.
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2 Programmable Flash/EPROM Chip Select.
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4 Programmable I/O Chip Select.
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2-level hardware key protection for Flash boot
block protection.
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24 bit address bus.
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EIDE Controller
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Compatible with EIDE (ATA-2).
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Backward compatibility with IDE (ATA-1).
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Supports up to 4 IDE devices
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Supports PIO and Bus Master IDE
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Concurrent channel operation (PIO & DMA
modes) - 4 x 32-Bit Buffer FIFO per channel
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Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.
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Bus Master with scatter/gather capability.
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Multi-word DMA support for fast IDE drives.
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Individual drive timing for all four IDE devices.
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Supports both legacy & native IDE modes.
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Supports hard drives larger than 528MB.
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Support for CD-ROM and tape peripherals.
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Integrated Peripheral Controller
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2X8237/AT compatible 7-channel DMA
controller.
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2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
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Three 8254 compatible Timer/Counters.
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Co-processor error support logic.
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Supports external RTC.
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Power Management
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Four power saving modes: On, Doze,
Standby, Suspend.
GENERAL DESCRIPTION
Release 1.3 - January 29, 2002
5/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1. GENERAL DESCRIPTION
At the heart of the STPC Elite is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, a high speed PCI local-bus controller
and Industry standard PC chip set functions
(Interrupt controller, DMA Controller, Interval timer
and ISA bus) and EIDE controller.
The processor bus runs at the speed of the
processor (x1 mode) or half the speed (x2 mode).
The STMicroelectronics x86 processor core is
embedded with standard and application specific
peripheral modules on the same silicon die. The
core has all the functionality of the ST standard
x86 processor products, including the low power
System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While
running in isolated SMM address space, the SMM
interrupt routine can execute without interfering
with the operating system or application
programs.
The `standard' PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated with the x86 processor core.
The PCI bus is the main data communication link
to the STPC Elite chip. The STPC Elite translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports generation of
Configuration cycles on the PCI bus. The STPC
Elite, as a PCI bus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PCI devices.
The STPC Elite integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Elite chip set through this bus.
An industry standard EIDE (ATA 2) controller is
built in to the STPC Elite and connected internally
via the PCI bus.
1.1. MEMORY CONTROLLER
The STPC handles the memory data (DATA) bus
directly, controlling from 8 to 128 MBytes. The
SDRAM controller supports accesses to the
Memory Banks to/from the CPU (via the host).
Parity is not supported.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (see
Table 1-1
)
The SDRAM Controller supports buffered or
unbuffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type
access.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
1.2. POWER MANAGEMENT
The STPC Elite core is compliant with the
Advanced Power Management (APM)
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit (PMU) module controls the power
consumption, providing a comprehensive set of
features that controls the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides the
following hardware structures to assist the
software in managing the system power
consumption:
- System Activity Detection.
Table 1-1. Memory configurations
Memory
Bank size
Number
Organisa
tion
Device
Size
1Mx64
4
1Mx16
16Mbits
2Mx64
8
2Mx8
4Mx64
16
4Mx4
4Mx64
4
2Mx16x2
64Mbits
8Mx64
8
4Mx8x2
16Mx64
16
8Mx4x2
4Mx64
4
1Mx16x4
8Mx64
8
2Mx8x4
32Mx64
16
4Mx4x4
16Mx64
8
2Mx16x2
128Mbits
32Mx64
16
4Mx8x4
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