Issue 2.2

1/61

STPC

CLIENT

PC Compatible Embedded Microprocessor

October 13, 2000

Figure 1. Logic Diagram

POWERFUL X86 PROCESSOR

64-BIT 66MHz BUS INTERFACE

64-BIT DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

UMA ARCHITECTURE

VIDEO SCALER

VIDEO OUTPUT PORT

VIDEO INPUT PORT

CRT CONTROLLER

135MHz RAMDAC

2 OR 3 LINE FLICKER FILTER

SCAN CONVERTER

PCI MASTER / SLAVE / ARBITER

ISA MASTER/SLAVE

IDE CONTROLLER

DMA CONTROLLER

INTERRUPT CONTROLLER

TIMER / COUNTERS

POWER MANAGEMENT

STPC CLIENT OVERVIEW

The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller, a
graphics subsystem, a video pipeline, and
support logic including PCI, ISA, and IDE
controllers to provide a single Consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video input stream
and mixing of the video stream with non-video
data from the frame buffer. The chip also includes
anti-flicker filters to provide a stable, high-quality
Digital TV output.
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).

PBGA388

x86

Core

Host I/F

DRAM

VIP

PCI

PCI BUS

ISA

EID

PCI

ISA BUS

CRT

Monitor

TV Output

SYNC Output

Col-

our

Vid-

CCIR Input

EIDE

Anti-

IPC

STPC CLIENT

2/61

Issue 2.2 - October 13, 2000

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86 proc-
essor with DOS, Windows and UNIX compat-
ibility.

Can access up to 4GB of external memory.

KBytes unified instruction and data cache
with write back and write through capability.

Parallel processing integral floating point unit,
with automatic power down.

Clock core speeds up to of 75 MHz.

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 3.3V operation.

DRAM Controller

Integrated system memory and graphic frame
memory.

Supports up to 128 MBytes system memory
in 4 banks and as little as MBytes.

Supports 4MBytes, 8MBites, 16MBites,
32MBites single-sided and double-sided
DRAM SIMMs.

Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.

Four 4-word read buffers for PCI masters.

Supports Fast Page Mode & EDO DRAMs.

Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.

60, 70, 80 & 100ns DRAM speeds.

Memory hole size of 1 MByte to 8 MBytes
supported for PCI/ISA buses.

Hidden refresh.

To check if your memory device is supported by
the STPC, please refer to

Table 6-69

in the

Programming Manual.

Graphics Controller

64-bit windows accelerator.

Backward compatibility to SVGA standards.

Hardware acceleration for text, bitblts, trans-
parent blts and fills.

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8-, 16-, and 24-bit pixels.

CRT Controller

Integrated 135MHz triple RAMDAC allowing
up to 1024 x 768 x 75Hz display.

8-, 16-, 24-bit per pixels.

Interlaced or non-interlaced output.

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Colour space conversion (RGB to YUV and
YUV to RGB).

Programmable window size.

Chroma and colour keying allowing video
overlay.

Programmable two tap filter with gamma cor-
rection or three tap flicker filter.

Progressive to interlaced scan converter.

Video Input port

Decodes video inputs in ITU-R 601/656 com-
patible formats.

Optional 2:1 decimator

Stores captured video in off setting area of
the onboard frame buffer.

Video pass through to the onboard PAL/
NTSC encoder for full screen video images.

HSYNC and B/T generation or lock onto
external video timing source.

PCI Controller

Integrated PCI arbitration interface able to
directly manage up to 3 PCI masters at a
time.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to
PCI.

Support for burst read/write from PCI master.

The PCI clock runs at a third or half CPU
clock speed.

STPC CLIENT

Issue 2.2 - October 13, 2000

3/61

ISA master/slave

The ISA clock generated from either
14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for
ISA cycles

Supports I/O recovery time for back to back I/
O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.

Supports flash ROM.

Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.

IDE Interface

Supports PIO

Supports up to Mode 5 Timings

Supports up to 4 IDE devices

Individual drive timing for all four IDE devices

Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFO per channel

Support for PIO mode 3 & 4

Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

Integrated peripheral controller

2X8237/AT compatible 7-channel DMA con-
troller.

2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Power Management

Four power saving modes: On, Doze, Stand-
by, Suspend.

Programmable system activity detector

Supports SMM.

Supports STOPCLK.

Supports IO trap & restart.

Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.

Supports RTC, interrupts and DMAs wake-up

UPDATE HISTORY FOR OVERVIEW

Issue 2.2 - October 13, 2000

5/61

UPDATE HISTORY FOR OVERVIEW

The following changes have been made to the Board Layout Chapter on 02/02/2000.

The following changes have been made to the Board Layout Chapter from Revision 1.0 to Release 1.2.

Section

Change

Text

Added

To check if your memory device is supported by the STPC, please refer to

Table 6-69 Host Address to MA Bus Mapping

in the Programming Manual.

Section

Change

Text

N/A

Replaced

"fully PC compatible" With "with DOS, Windows and UNIX compatibility"

N/A

Replaced

"133 MHz

" With 75 MHz"

N/A

Removed

"Drivers for Windows and other operating systems."

N/A

Removed

Requires external frequency synthesizer and reference sources."

N/A

Replaced

Chroma and colour keying for integrated video overlay

." With "Chroma and colour

keying

allowing

video overlay.

N/A

Replaced

"Accepts video inputs in CCIR 601/656 or ITU-R 601/656, and decodes the
stream

." With "

Decodes

video inputs in ITU-R 601/

656 compatible formats

N/A

Replaced

"Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3 masters can connect directly.
External PAL allows for greater than 3 masters."

With

"Integrated PCI arbitration interface able to directly manage up to 3 PCI
masters at a time."

N/A

Replaced

"0.33X and 0.5X CPU clock PCI clock." With "The PCI clock runs at a third or
half CPU clock speed."

N/A

Removed

"Supports flash ROM."

N/A

Replaced

"Supports ISA hidden refresh." With "Supports flash ROM."

N/A

Replaced

Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI

and Host bus. NSP compliant." With "Buffered DMA & ISA master cycles to
reduce bandwidth utilization of the PCI and Host bus. "

N/A

Replaced

Supports PIO and Bus Master IDE" With "Supports PIO"

N/A

Removed

"Transfer Rates to 22 MBytes/sec"

N/A

Added

"Individual drive timing for all four IDE devices "

N/A

Replaced

"Concurrent channel operation (PIO & DMA modes) - 4 x 32-Bit Buffer FIFO
per channel"
With
"Concurrent channel operation (PIO modes) - 4 x 32-Bit Buffer FIFO per
channel"

N/A

Removed

"Support for DMA mode 1 & 2."
"Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers."
"Supports 13.3/16.6 MB/s DMA data transfers"
"Bus Master with scatter/gather capability "
"Multi-word DMA support for fast IDE drives "
"Individual drive timing for all four IDE devices "
"Supports both legacy & native IDE modes"
"Supports hard drives larger than 528MB"
"Support for CD-ROM and tape peripherals"
"Backward compatibility with IDE (ATA-1)."
"Drivers for Windows and other OSes"

Part Number STPCD01