1/6
PRELIMINARY DATA
October 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STP40NS15
N-CHANNEL 150V - 0.042
- 40A TO-220
MESH OVERLAYTM MOSFET
INTERNAL SCHEMATIC DIAGRAM
s
TYPICAL R
DS
(on) = 0.042
s
EXTREMELY HIGH dv/dt CAPABILITY
s
VERY LOW INTRINSIC CAPACITANCES
s
GATE CHARGE MINIMIZED
DESCRIPTION
This powermos MOSFET is designed using the
company's consolidated strip layout-based MESH
OVERLAY
TM
process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
s
HIGH CURRENT SWITCHING
s
UNINTERRUPTIBLE POWER SUPPLY (UPS)
s
PRIMARYSWITCH IN ISOLATED DC-DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
(·)Pulse width limited by safe operating area
TYPE
V
DSS
R
DS(on)
I
D
STP40NS15
150 V
<0.052
40A
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
150
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
150
V
V
GS
Gate- source Voltage
±20
V
I
D
Drain Current (continuos) at T
C
= 25°C
40
A
I
D
Drain Current (continuos) at T
C
= 100°C
25
A
I
DM
(
q
)
Drain Current (pulsed)
160
A
P
TOT
Total Dissipation at T
C
= 25°C
140
W
Derating Factor
0.933
W/°C
dv/dt
Peak Diode Recovery voltage slope
9
V/ns
T
stg
Storage Temperature
65 to 175
°C
T
j
Max. Operating Junction Temperature
175
°C
1
2
3
TO-220
STP40NS15
2/6
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
Rthj-case
Thermal Resistance Junction-case Max
1.07
°C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
°C/W
Rthc-sink
Thermal Resistance Case-sink Typ
0.5
°C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
°C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
40
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
500
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 µA, V
GS
= 0
150
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1
µA
V
DS
= Max Rating, T
C
= 125 °C
10
µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ±20V
±100
nA
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250µA
2
3
4
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 40 A
0.044
0.052
I
D(on)
On State Drain Current
V
DS
> I
D(on)
x R
DS(on)max,
V
GS
= 10V
40
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 20A
20
S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
2400
pF
C
oss
Output Capacitance
380
pF
C
rss
Reverse Transfer
Capacitance
160
pF
3/6
STP40NS15
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on Delay Time
Rise Time
V
DD
= 75V, I
D
= 20A
R
G
= 4.7
, V
GS
= 10V
(see test circuit, Figure 3)
25
ns
t
r
45
ns
Q
g
Total Gate Charge
V
DD
= 120V, I
D
= 40A,
V
GS
= 10V
100
110
nC
Q
gs
Gate-Source Charge
17
nC
Q
gd
Gate-Drain Charge
47
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(off)
Turn-off Delay Time
V
DD
= 75V, I
D
= 20A
R
G
= 4.7
, V
GS
= 10V
(see test circuit, Figure 3)
85
ns
T
f
Fall Time
t
r(Voff)
Off-voltage Rise Time
V
clamp
= 120V, I
D
= 20 A,
R
G
= 4.7
,
V
GS
= 10V
(see test circuit, Figure 5)
47
ns
t
f
Fall Time
35
ns
t
c
Cross-over Time
70
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
Source-drain Current
40
A
I
SDM
(2)
Source-drain Current (pulsed)
160
A
V
SD
(1)
Forward On Voltage
I
SD
= 40A, V
GS
= 0
1.5
V
t
rr
Reverse Recovery Time
I
SD
= 40A, di/dt = 100A/µs,
V
DD
= 50V, T
j
= 150°C
(see test circuit, Figure 5)
270
ns
Q
rr
Reverse Recovery Charge
200
nC
I
RRM
Reverse Recovery Current
1.5
A
STP40NS15
4/6
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
5/6
STP40NS15
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
0.107
D1
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
0.409
L2
16.4
0.645
L4
13.0
14.0
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
STP40NS15
6/6
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
© 2000 STMicroelectronics Printed in Italy All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
PDF 
ZIP