COMPLETE CHIP SET FOR ADSL MODEM

FUNCTIONS

COMPLIANCE WITH ANSI T1.413 ISSUE 1 &

ISSUE 2

IMPLEMENTS

DISCRETE

MULTITONE

(DMT) MODULATION AND DEMODULATION

DATA RATES UP TO 8Mbps DOWNSTREAM

AND TO 1Mbps UPSTREAM WITH 32Kbps
GRANULARITY

BUILT-IN ATM TRANSPORT
SUPPORT

ADAPTIVE

RATE

MODE

32Mbps INCREMENTS

APPLICABLE AT BOTH ENDS OF LOOP:

ATU-C (LT) AND ATU-R (NT)

255 CARRIERS WITH 4.3125KHz SPACING
DEDICATED SOFTWARE DRIVER AVAIL-

ABLE

PROCESSOR INDEPENDENT C++ SOURCE

COMPILATION

FREQUENCY

DIVISION

MULTIPLEXING

(FDM) FOR HIGH ROBUSTNESS IN PRES-
ENCE OF CROSSTALK

REED-SOLOMON FORWARD ERROR COR-

RECTION

TRELLIS CODER AND DECODER
PROGRAMMABLE SIMULTANEOUS SUP-

PORT OF INTERLEAVED AND NON-INTER-
LEAVED CHANNELS (DUAL LATENCY)

FULL, REDUCED AND MINIMAL ATM OVER-

HEAD FRAMING MODES

BIT STREAM MODE CAPABLITY FOR STM

TRANSPORT

DIRECT CONNECTION TO ATM SYSTEMS

VIA UTOPIA INTERFACE (LEVEL 1 OR 2)

MICROCONTROLLER INTERFACE WITH 16

BITS MULTIPLEXED ADDRESS/DATA BUS

LOW POWER TECHNOLOGY: 1.3w TOTAL
SINGLE 3.3V POWER SUPPLY
-40 TO +85

c OPERATING TEMP RANGE

Applications

HIGH SPEED INTERNET ACCESS
REMOTE ACCESS TO CORPORATE NET-

WORK

FOR

TELECOMMUTERS

AND

BRANCH OFFICES

VIDEO-ON-DEMAND OVER TWISTED PAIR

ADSL MODEMS, DSLAMs, ROUTERS, AND
CONCENTRATORS
ADSL PC NIC's
LITE-ADSL T1.413 BASED FOR NT-SIDE
SPLITTERLESS APPLICATIONS

GENERAL DESCRIPTION

The ADSL modem chip set with ATM interface
provides all the active functions required to build
a complete ATM-based ADSL modem from line
interface to ATM UTOPIA bus. The chip set em-
ploys Discrete MultiTone modulation as specified
in ANSI T1.413. The chip set can operate at
either end of the loop (in ATU-C or ATU-R mode)
with only changes in the microcontroller code.
Reed-Solomon forward error correction plus Trel-
lis coding with or without interleaving in internal
interleaving RAM provides maximum noise immu-
nity.

This is preliminary information on a new product now in development. Details are subject to change without notice.

November 1998

ORDERING NUMBERS: STLC60134 (TQFP64)

STLC60135 (PQFP144)

STLC60134
STLC60135

ADSL MODEM CHIP SET

PRODUCT PREVIEW

TQFP64

PQFP144

DMT

MODEM

STLC60135

UTOPIA

CONTROL

MEM

AFE

UTP

STLC60134

D98TL390

Figure 1. ADSL modem block configuration.

1/7

Interleaving is optional and can be used simulta-
neously on a slow channel (e.g., for data or con-
trol info) while a fast channel (e.g., video) oper-
ates

without

interleaving.

ICs

include

rate

adaptation capabilities during show time.
In transmit direction the chip set allows to select
an attenuation of the signal in case of short loops
or large echo (politeness). In receive direction the
chip set can optionally control an external multi-
plexer to select an external attenuation of the sig-
nal in case of short loops.

TOSCA chip set
TOSCA is a two-chip ADSL modem transceiver.
ST also provides the necessary software for
transceiver's external controller.
TOSCA can easily be hooked up with ATM sys-
tems through the built-in UTOPIA level 2 inter-
face. That allows ATM traffic to be carried, at up
to 8Mbit/s downstream and 1Mbit/s upstream,
over a very plain and widespread twisted pair.
TOSCA can be used at both ends of the loop
(ATU-C and ATU-R ends).

The modem control software can be compiled as
C++ code, independently on the processor used.
The driver can be interfaced to any external real
time operating system.
These pages block diagrams show the main func-
tions built-in in STLC60134 and STLC60135.

TOSCA chip set supports three different rate ad-
aptation modes: fixed rate adaptation mode, fixed
with capability to boost within fixed range, dy-
namic rate adaptation during show time.
Modem's performances are set by the following

parameters: Rate adaptation mode, Downstream
and Upstream bit rate for both latency paths,
Noise margins (min, max and target typically at
10E-7 BER without RS, interleaving and trellis),
Maximum power spectral density for downstream,
Maximum power for both up and downstream,
Carrier mask (which tones are disabled), maxi-
mum interleaving delay.
Tones from number 8 to number 255 can be
used: from 8 to 31 for upsteam signals and from
32 to 255 for downstream signals. Numbers 16
and 64

are dedicated to pilot tones which are

employed for synchronisation purposes between
ATU-C and ATU-R ends. The software sets the
use of tones for optimisation of performances.
At ATU-R, time recovery is carried out by the
chip-set through the pilot tones. This activity is
undertaken in two steps in order to achieve no
more than 2ppm between ATU-C and ATU-R.
The transceiver controller software monitors line
and channel. As far as line is concerned noise
margin, attenuation, power, carrier load, relative
capacity occupation are checked. Channel's
monitoring deals with cell-delineation, actual ATM
(fast and interleaved) up and downstream rates,
achievable ATM DS and US rates (only at ATU-C
side).

TOSCA ICs
TOSCA consists

of an

Analog Front End

(STLC60134) and a Discrete Multitone Modem
(STLC60135) integrated circuits which are pro-
duced by STMicroelectronics.
Here below we will briefly go through the main
topics of both the ICs.

DAC

MUX

12 bits/8.8MHz

DAC

MUX

12 bits/8.8MHz

ADC

MUX

12 bits/8.8MHz

TRANSMIT-SIDE

LPF

1.1MHz

LPF

138KHz

LPF

1.1MHz

LPF

138KHz

ATU-R

ATU-C

LPF

138KHz

LPF

1.1MHz

ATU-R

ATU-C

VCODAC

XTAL

DRIVER

G=15...0dB

STEP 1dB

G=15...0dB

STEP 1dB

35.328MHz

G=0...31dB

STEP 1dB

D98TL391

AGC

LNA

RECEIVE-SIDE

Figure 2. Analog Front End block diagram.

TOSCA STLC60134/STLC60135

2/7

Analog Front End (STLC60134)
HCMOS5A (0.5

m) mixed digital and analog

technology has been chosen to produce this
component that embodies the analog functions of
the TOSCA. Automatic gain control amplifiers,
placed at the analog functions of the TOSCA.
Automatic gain control amplifiers, placed at the
analog interface of transmit and receive paths, al-
low for line's high attenuation in order to keep ac-
ceptable noise level of the signal ADC's and
DAC's resolution, that is 12-bit wide with 8.8MHz
sampling rate. Thanks to the symmetrical archi-
tecture the same channel filter can be used as a
part of either the upstream or the downstream
path: ATU-C or ATU-R end.
A built-in driver allows for single external clock
generation using a XTAL (ATU-C) or a VCXO
(ATU-R).

STLC60134 Analog Front End's main features:

Rx automatic gain control: 0-31dB in 1dB

steps

Two input ports allow selection of RX signals,

e.g. with or without external attenuation

Second transmit port available (i.e. echo can-

cellation)

Programmable low pass and band pass filters
12-bit DAC and ADC, sampling at 8.832MHz
Xtal: 35.328MHz,

50ppm, the accuracy of the

frequency is determined by the External XTAL

Direct connection to STLC60135 DTM modem
Error correction on ADC output
Test interface for digital and analog sections
Analog and digital loop back modes

Single 3.3V supply, or 3.3V analog and 3.0V
digital supplies
Power dissipation 0.4W
Power-down mode 0.1W
TQFP-64 (10 x 10mm body, 0.5mm pitch)

Discrete MultiTone Digital Modem (STLC60135)
The DMT modem has been developed in
HCMOS6 (0.35

m) technology.

It performs PMD (Physycal Medium Dependant)
sub-layer and TC (Transmission Convergence)
sub-layer functions. In other words we can think
to split up the chip into two separate blocks: the
first one which carries out modem functions
(PMD sub layer) and a second one in charge of
ATM framing.
The chip is controlled and programmed by an ex-
ternal processor and is seen as a memory
mapped device.

MODEM Functions

The modem part of the chip includes all the nec-
essary blocks needed for digitally DMT mapping
and demapping. A 14-bit code for every carrier al-
lows constellations with up to 16383 points.
Internally digital filters carry out Time Equalization
to reduce the effects of the inter symbol inter-
faces. That is followed by Fast Fourier Transform
(in transmit direction an Inverse FFT is per-
formed) in order to change from time domain to
frequency domain.

Afterwards a

Frequency

Equalization cuts down carrier by carrier the
channel distortion; signal's amplitude attenuation
and phase rotation. By efficient algorithms, this

DSP FE

TC SUBLAYER

CELL

BASED

FUNCT.

ADSL

AFE

INTERF.

D98TL406

DSP FE

FFT

DEMAPPER

VITERBI

R/S

DECODER

DE-

FRAMER

ATM (UTOPIA)

IFFT

MAPPER

VITERBI

SIGNAL

MONITORING &
FEQ UPDATE &

DPLL

PMD SUBLAYER

R/S

CODER

FRAMER

CELL

BASED

FUNCT.

INTERF.

INTERLEAVED

FAST

INTERLEAVED

Figure 3. DMT Modem block diagram.

TOSCA STLC60134/STLC60135

3/7

block drives, through the STLC60134's integrated
VCXO controller, the NT crystal oscillator which
comes up in an excellent synchronisation (less
than 2ppm) between ATU-C and ATU-R.

FRAMING Functions
STLC60135 performs framing functions for ge-
neric and ATM TC sub layers.
ATM TC sub layer performs cell level functions: de-
lineation, idle cells or unassigned cells insertion/ex-
traction, payload scrambling, Header Error Correc-
tion (HEC) check and data frame generation.

In order to comply with T1.413 Issue 2 rules and
full interoperability with other manufacturers' mo-
dems (providing they guarantee compliance with
either Issue 1 or Issue 2) framing features (such
as interleaving and fast mode) are implemented
with programmable parameters.
ATM frames can be bypassed in order to carry
non-ATM bit streams, which makes the chip set
very fit for applications using dedicated framing
such as Frame-relay, etc.

STLC60135 DTM modem main features:

Time-domain equalisation
Decimation, interpolation,
FFT and IFFT, with different length and sam-

pling rate at ATU-C and ATU-R side

Rotor and frequency-domain equalisation
Mapping/demapping
Trellis coding and decoding using Viterbi algo-

rithm

Error and noise monitoring on individual tones
Reed-Solomon encoding and decoding
(De) framing and (de) interleaving
Cell HEC generation/verification
Payload (de) scrambling
ATM cell insertion/extraction
Idle &/or Unassigned cell insertion/filtering
VPI/VCI filtering
UTOPIA interface (Level 1 or 2)
Microcontroller interface with 16-bit multi-

plexed address/data bus and big/little endian
format supported

JTAG test port
Single 3.3V supply, 1.0W
PQFP144 (28 x 28mm body, 0.65mm pitch)

ADSL Modem control software
The ADSL transceiver is based on a programma-
ble DMT modem (STLC60135) whose configura-
tion is loaded by an external controller.

Additionally the control functions, STMicroelec-
tronics provides the DTM modem software. The
software is written in C++ language, and is de-
signed to be portable to any processor.
The driver has to be interfaced with a real time
OS kermel, it is compatible with any standard
product available on the market. The kernel man-
ages the tasks dedicated to modem software.
The modem 5W core comes with three additional
two software modules: a Board Support Package
(BSP) and two Application Program Interfaces
(API). BSP manages the hardware dependent
features (i.e. interrupts, peripheral mapping).

APIs interface to the higher level application soft-
ware and to the OS.

ADSL Loop performances
The hereafter tables show the performances that
a system, which houses TOSCA, can achieve for
ANSI and ETSI loops. The following results refer
to an end-to end ADSLequipment with no exter-
nal disturbance.

ANSI Loop (26awg)

Length

Downstream

Upstream

9Kft

7.47 E +0.6

1.05 E +06

12Kft

3.69 E +0.6

9.37 E +05

15Kft

1.56 E +0.6

7.25 E +05

ETSI Loop (Loop 2, noise model A)

Length

Downstream

Upstream

2Km

8.00 E +0.6

8.32 E +05

4Km

4.07 E +0.6

6.72 E +05

5Km

1.70 E +0.6

4.72 E +05

USER HIGH LEVEL SOFTWARE

ADSL MANAGEMENT APPLICATION SW

OS INTERFACE

MODEM SW

BOARD SUPPORT PACKAGE

ADSL HARDWARE

D98TL392

Figure 4. Software Architecture.

TOSCA STLC60134/STLC60135

4/7

TQFP64

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.40

1.45

0.053

0.055

0.057

0.18

0.23

0.28

0.007

0.009

0.011

0.12

0.16

0.20

0.0047 0.0063 0.0079

12.00

0.472

10.00

0.394

7.50

0.295

0.50

0.0197

12.00

0.472

10.00

0.394

7.50

0.295

0.40

0.60

0.75

0.0157 0.0236 0.0295

1.00

0.0393

0°

(min.), 7

(max.)

TQFP64

Seating Plane

0.10mm

OUTLINE AND

MECHANICAL DATA

TOSCA STLC60134/STLC60135

5/7

Part Number STLC60134