STLC5444

QUAD FEEDER POWER SUPPLY

SUPPLIES POWER FOR UP TO FOUR DIGI-

TAL TELEPHONE LINES

CONFORMS TO THE CCITT RECOMMEN-

DATIONS FOR POWER FEED AT THE S OR
T REFERENCE POINTS

SUPPORTS POINT-TO-POINT AND POINT

TO MULTIPOINT CONFIGURATIONS

EACH OF THE FOUR LINES IS INDIVIDU-

ALLY CONTROLLED

HIGH-VOLTAGE BCD TECHNOLOGY SUP-

PORTING UP TO -130V

AUTOMATIC THERMAL SHUTDOWN
STATUS CONDITION DETECTION (BY MI-

CROPROCESSOR) FOR EACH LINE:
Low output voltage
Openloop
Current overload
Thermal overload
Normal line condition

PROGRAMMABLE CURRENT LIMITING
OUTPUT CURRENT UP TO 120mA

DESCRIPTION
The ISDN Quad Feeder Power Supply (IQFPS)
provides a power source for up to four line inter-
faces. The power source to the device is a local
battery or a centralized regulated power supply.
It can operate in point-to-point and point-to-mul-
tipoint configurations as far as S interface is con-
cerned.
By the device microprocessor interface, each
powered line is individually controlled and moni-
tored.
Therefore, overloads and faults are easy to detect
and localize even in a large system.
The status conditions detected by the device on
each line that may be read by the microprocessor
are :

low output voltage
openloop
current overload
thermal overload
normal line conditions

A hardware current limiting programmable feature
is available.

December 1997

DIP24

PLCC44

ORDERING NUMBERS: STLC5444B1 (DIP24)

STLC5444FN (PLCC44)

ILIM

N.C.

VBB

N.C.

VBB

RSRVD

RESET

D94TL102

INT

BGND

VCC

ALE

DGND

DIP24 PIN CONNECTION (Top view)

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44 43

24 25

N.C.

INT

VBB

N.C.

VBB

N.C.

VBB

N.C.

BGND

N.C.

ILIM

VCC

N.C.

VBB

N.C.

VBB

N.C.

DGND

N.C.

ALE

RESET

VBB

N.C.

VBB

N.C.

D94TL103

PLCC44 PIN CONNECTION (Top view)

MUX

INDIRECT

ADDRESS

INTERFACE

ADDRESS

BUS 0/2

BIT 3

INT EN

OUTPUT

BUS D3/D0

IAR EN

LINE

ENABLE

INPUT BUS D3/D0

VOLTAGE

REFERENCE

DRIVERS

STATUS

DETECTOR

STATUS GROUP BUS

LINE ENABLE REGISTER BUS

LER EN

S DRIVERS

DISABLE

O/3

D94TL104B

THERMAL

OVERLOAD

LINE

STATUS

BUS

ALE

D3/D0

INT

RESET

ILIM

VBB(8)

VCC

DGND

BGND

VBB(12)

BLOCK DIAGRAM

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PIN DESCRIPTION

Name

PLCC

DIP

Function

Bit 1 of the tri state I/O data bus

2,4,8,10,

13,14,
16,18,
20,23,
25,26,
28,34,

37,38,44

7,9

No connection

Bit 0 of the tri state I/O data bus

INT

Active low interrupt output for the

P (open drain)

VBB

6,7

15,17

22,29,

39,40

8,12

Battery supply line (negative battery`s terminal)

BGND

Battery ground line

VCC

+5V supply line

ILIM

Current limit programming

Output of the power switch controller 0

Output of the power switch controller 1

Output of the power switch controller 2

RSRVD

Reserved pin: it must be left floating

Output of the power switch controller 3

RESET

Active high reset input

Active low read input

Active low chip select input

Active low write input

ALE

Active high address latch enable

DGND

Digital ground

Address bit for R/W operations on the data bus

Bit 3 of the I/O tri state data bus

Bit 2 of the I/O tri state data bus

FUNCTIONAL DESCRIPTION

ADDRESS LINE (Input)
A0 selects source and destination locations for
read and write operations on the data bus. A0
must be valid on the falling edge of ALE or during
RD and WR if ALE is tied High.

ALE - Address Latch Enable (Input; Active
High)

ALE is an input control pulse used to strobe the
address on the A0 line into the address latch.
This signal is active High to admit the input ad-
dress. The address is latched on the High-Low
transition of ALE. While ALE is High, the address
latch is transparent. For an unmultiplexed micro-
processor bus, ALE must be tied High.

BGND - Ground Battery

CS - Chip Select (Input; Active Low)
CS must be Low to enable the read or write op-
erations of the device. Data transfer occurs over
the D3-D0 lines.

D3-D0 - DATA BUS (Input/Output; Three-State)
The four bidirectional data bus lines are to ex-
change information with a microprocessor. D0 is
the least significant bit and D3 is the most signifi-
cant bit. A High on the data bus corresponds to a
logical 1. These lines act as input when WR and
CS are active and as output when RD and CS are
active. When CS is inactive, the D3-D0 pins are
placed in a high-impedance state.

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FUNCTIONAL DESCRIPTION (continued)

DGND - Ground Digital

ILIM - Current Limit Programming (Input)
ILIM programs the current limit of the Output driv-
ers using an external resistor connected between
ILIM and VBB. The ILIM pin is 1.25V more posi-
tive than VBB. The current limit is 5mA plus 1000
times the current in the external resistor. The pro-
grammed current limit applies to each driver.

INT - Interrupt (Output; Open-Collector, Active
Low)
INT augments the Microprocessor Interface by
generating an interrupt when a Current Overload
Detector (COD) occurs. INT is active whenever
any bits in the COD register are active. INT is not
latched; when the COD register is zero, INT goes
inactive (High). INT will also go inactive if the
IQFPS automatically disables the S-output driver
that caused the interrupt (due to Thermal Over-
load), or if the microprocessor disables that line
via the Line Enable Register (LER). COD inter-
rupts can be masked via the Indirect Address
Register (IAR); RESET always disables the INT
pin.

RD - Read (Input; Active Low)
The active Low read signal is conditioned by CS
and transfers internal information to the data bus.
If A0 is a logical 0, logic levels of the Indirect Ad-
dress Register (IAR) and Thermal Shutdown
Status bit will be transferred to D3-D0. If A0 is a
logical 1, the data addressed by the IAR will be

transferred to D3-D0.

RESET - Reset (Input; Active High)

RESET initialize the registers in the device, leav-
ing the drivers switched off.

S3-S0 - Drivers (Output)
S3-S0 each supply power to one line. The outputs
can sink up to 120 mA each. The voltage at the
line is connected to VBB through a DMOS switch.

VBB - Battery Voltage (input)
VBB is the internal negative supply voltage. VBB
must always be connected to the most negative
supply voltage. The MPI Registers will not func-
tion properly when the battery power is discon-
nected, that is, when VBB is floating or grounded.
The IQFPS should also be reset if a drastic tran-
sient is applied to VBB.

VCC - +5V Power Supply (Input)

WR - Write (Input; Active Low)
The active Low write signal is conditioned by CS
and transfers information from the data bus to an
internal register selected by A0. If A0 is a logical
1, D3-D0 is written into the Line Enable Register
(LER). If A0 is a logical 0, D3-D0 is written into
the IAR. LER and IAR are the only two writable
registers in the device.

STLC5444

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DC CHARACTERISTICS (V

= -54V; V

= 5V; unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Input Voltage High Level

Input Voltage Low Level

0.8

High Level Output Current

= 2.4V

400

Low Level Output Current

= 0.4V

High Level Input Current

= 2V

Low Level Input Current

= 0.8V

OZH

Output Hi-Z Current High

2.4V < V

< V

OZL

Output Hi-Z Current Low

0V < V

< 0.4V

supply Current

1.4

Logic I/O Capacitance

SAT

Saturation Voltage

= 80mA

Output DMOS Saturation Resistivity

= 80mA

Supply Current

= -54V, R

LI M

= 26.6K

Output Disabled

3.2

SLIM

Delta Limit Current vs.
Theoretical Programmed Value
I

SLIM

LIM

= 26.6K

, V

= -96V

LIM

= 10.9K

, V

= -54V

10%

LVD

Low Voltage Detector Threshold
(relative to V

)

S3 - S0 output active

2.7

3.3

SOL

Current Overload Detector
Threshold (as % of I

SLIM

)

SOC

Open Loop Detector Threshold

1.5

Si Leakage Current to ground @
Si disabled

= -110V

100

LVD

Low Voltage Detector Hysteresis

200

OLD

Open Loop Detector Hysteresis

0.6

1.6

COD

Current Overload Detector
Hysteresis

2.4

4.0

130

C Thermal Detector

Hysteresis

160

C Thermal Detector

Hysteresis

Thermal Overload Recovery
Time H1

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Part Number STLC5444