MK41T56
MKI41T56
512 bit (64b x8) Serial Access TIMEKEEPER
®
SRAM
March 1999
1/15
COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH and YEARS
SOFTWARE CLOCK CALIBRATION
AUTOMATIC POWER-FAIL DETECT and
SWITCH CIRCUITRY
I
2
C BUS COMPATIBLE
56 BYTES of GENERAL PURPOSE RAM
ULTRA-LOW BATTERY SUPPLY CURRENT of
500nA
OPERATING TEMPERATURE:
MK41T56: 0 to 70
°
C
MKI41T56: 40 to 85°C
AUTOMATIC LEAP YEAR COMPENSATION
DESCRIPTION
The MK41T56 TIMEKEEPER
®
is a low power 512
bit static CMOS RAM organized as 64 words by 8
bits. A built-in 32.768 kHz oscillator (external crystal
controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured
in binary coded decimal (BCD) format. Addresses
and data are transferred serially via a two-line
bi-directional bus. The built-in address register is
incremented automatically after each write or read
data byte. The MK41T56 clock has a built-in power
sense circuit which detects power failures and
automatically switches to the battery supply during
power failures. The energy needed to sustain the
RAM and clock operations can be supplied from a
small lithium button cell.
AI02304
OSCI
VCC
MK41T56
MKI41T56
VSS
SCL
OSCO
SDA
FT/OUT
VBAT
Figure 1. Logic Diagram
OSCI
Oscillator Input
OCSO
Oscillator Output
FT/OUT
Frequency Test / Output Driver
(Open Drain)
SDA
Serial Data Address Input / Output
SCL
Serial Clock
V
BAT
Battery Supply Voltage
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
8
1
PSDIP8 (N)
0.4mm Frame
8
1
SO8 (S)
150mil Width
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
MK41T56
MKI41T56
0 to 70
40 to 85
°
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
55 to 125
°
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
0.25
W
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
SDA
VSS
SCL
FT/OUT
OSCO
OSCI
VCC
VBAT
AI02305
MK41T56
MKI41T56
1
2
3
4
8
7
6
5
Figure 2A. DIP Pin Connections
1
SDA
VSS
SCL
FT/OUT
OSCO
OSCI
VCC
VBAT
AI02306
MK41T56
MKI41T56
2
3
4
8
7
6
5
Figure 2B. SOIC Pin Connections
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
0
ST
10 Seconds
Seconds
Seconds
00-59
1
X
10 Minutes
Minutes
Minutes
00-59
2
X
X
10 Hours
Hours
Hour
00-23
3
X
X
X
X
X
Day
Day
01-07
4
X
X
10 Date
Date
Date
01-31
5
X
X
X
10 M.
Month
Month
01-12
6
10 Years
Years
Year
00-99
7
OUT
FT
S
Calibration
Control
Keys: S = SIGN Bit; FT = FREQUENCY TEST Bit; ST = STOP Bit; OUT = Output level; X = Don't care.
Table 3. Register Map
2/15
MK41T56, MKI41T56
Data retention time is in excess of 10 years with a
50mAh 3V lithium cell. The MK41T56 is supplied in
8 pin Plastic Dual-in-Line and 8 lead Plastic SOIC
packages.
OPERATION
The MK41T56 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (11010000). The 64 bytes contained in the
device can then be accessed sequentially in the
following order:
1.
Seconds Register
2.
Minutes Register
3.
Hours Register
4.
Day Register
5.
Date Register
6.
Month Register
7.
Years Register
8.
Control Register
9 to 64.
RAM
DESCRIPTION (cont'd)
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI00586C
SECONDS
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
OSCI
OSCO
FT/OUT
VCC
VSS
VBAT
SCL
SDA
1 Hz
Figure 3. Block Diagram
3/15
MK41T56, MKI41T56
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±
10
µ
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±
10
µ
A
I
CC1
Supply Current
SCL/SDA = V
CC
0.3V
1
mA
I
CC2
Supply Current (Standby)
1
mA
V
IL
Input Low Voltage
0.3
1.5
V
V
IH
Input High Voltage
3
V
CC
+ 0.8
V
V
OL
Output Low Voltage
I
OL
= 5mA, V
CC
= 4.5V
0.4
V
V
BAT
(1)
Battery Supply Voltage
2.6
3
3.5
V
I
BAT
Battery Supply Current
T
A
= 25
°
C, V
CC
= 0V,
Oscillator ON, V
BAT
= 3V
450
500
nA
Note: 1. The RAYOVAC BR1225 or equivalent is recommended as the battery supply.
Table 6. DC Characteristics
(T
A
= 0 to 70
°
C or 40 to 85
°
C; V
CC
= 4.5V to 5.5V)
Symbol
Parameter
Min
Max
Unit
C
IN
Input Capacitance (SCL)
7
pF
C
OUT
(2)
Output Capacitance (SDA, FT/OUT)
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled, not 100% tested.
3. Outputs deselected.
Table 5. Capacitance
(1,2)
(T
A
= 25
°
C, f = 1 MHz )
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
1.2 V
BAT
1.25 V
BAT
1.285 V
BAT
V
V
SO
Battery Back-up Switchover Voltage
V
BAT
V
Note: 1. All voltages referenced to V
SS
.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
°
C or 40 to 85
°
C)
Symbol
Parameter
Min
Typ
Max
Unit
f
O
Resonant Frequency
32.768
kHz
R
S
Series Resistance
35
k
C
L
Load Capacitance
12.5
pF
Notes:
Load capacitors are integrated within the MK41T56. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
STMicroelectronics recommends the ECS-.327-12.5-8SP-2 quartz crystal is recommended for industrial temperature operations.
ESC Inc. can be contacted at 800-237-1041 or 913-782-7787 for further information on this crystal type.
Table 8. Crystal Electrical Characteristics
(Externally Supplied)
4/15
MK41T56, MKI41T56
Symbol
Parameter
Min
Max
Unit
t
PD
SCL and SDA at V
IH
before Power Down
0
ns
t
FB
V
PFD
(min) to V
SO
V
CC
Fall Time
300
µ
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
100
µ
s
t
REC
SCL and SDA at V
IH
after Power Up
200
µ
s
Table 9. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
°
C or 40 to 85
°
C)
AI00595
VCC
tFB
tREC
tPD
tRB
VPFD
VSO
DATA RETENTION TIME
SDA
SCL
IBAT
Figure 5. Power Down/Up Mode AC Waveforms
OPERATION (cont'd)
The clock continually monitors V
CC
for an out of
tolerance condition. Should V
CC
fall below V
PFD
,
the device terminates an access in progress and
resets the device address counter. Inputs to the
device will not be recognized at this time to prevent
erroneous data from being written to the device
from an out of tolerance system. When V
CC
falls
below V
BAT
, the device automatically switches over
to the battery and powers down into an ultra low
current mode of operation to conserve battery life.
Upon power-up, the device switches from battery
to V
CC
at V
BAT
and recognizes inputs when V
CC
goes above V
PFD
volts.
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock
signals (SCL). Both the SDA and the SCL lines
must be connected to a positive supply voltage via
a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the
bus is not busy.
During data transfer, the data line must remain
stable whenever the clock line is High.
Changes in the data line while the clock line is
High will be interpreted as control signals.
5/15
MK41T56, MKI41T56
PDF 
ZIP