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DATA BRIEFING

June 2000

Complete data available on

Data-on-Disc CD-ROM or at www.st.com

M88 FAMILY

In-System Programmable (ISP) Multiple-Memory and

Logic FLASH+PSD Systems (with CPLD) for MCUs

Single Supply Voltage:
5 V

10% for M88xxFxY

3 V (+20/10%) for M88xxFxW

1 or 2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)

A second non-volatile memory:
256 Kbit (32K x 8) EEPROM (for M8813F1x)

or Flash memory (for M88x3F2x)

4 uniform sectors (8K x 8)

SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)

Over 3,000 Gates of PLD: DPLD and CPLD

27 Reconfigurable I/O ports

Enhanced JTAG Serial Port

Programmable power management

Stand-by current:
50

A for M88xxFxY

A for M88xxFxW

High Endurance:
100,000 Erase/Write Cycles of Flash Memory
10,000 Erase/Write Cycles of EEPROM
1,000 Erase/Write Cycles of PLD

DESCRIPTION
The FLASH+PSD family of memory systems for
microcontrollers

(MCUs)

brings

In-System-

Figure 1. Logic Diagram

AI02856

AD0-AD15

PC0-PC7

VCC

FLASH+PSD

VSS

PD0-PD2

PB0-PB7

PA0-PA7

CNTL0-

CNTL2

RESET

Table 1. Signal Names

PA0-PA7

Port-A

PB0-PB7

Port-B

PC0-PC7

Port-C

PC2 = Voltage Stand-by

PD0-PD2

Port-D

AD0-AD15

Address/Data

CNTL0-CNTL2

Control

RESET

Reset

Supply Voltage

Ground

PLCC52 (K)

PQFP52 (T)

M88 FAMILY

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Figure 2A. PLCC Connections

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

CNTL2

RESET

CNTL0

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

VCC

AD7

AD6

AD5

AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

VCC

GND

PC3

PC2

PC1

PC0

AI02857

Figure 2B. PQFP Connections

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

32 AD8

31 V

30 AD7

29 AD6

28 AD5

27 AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

GND

PC3

PC2

PC1

PC0

PB0

PB1

PB2

PB3

PB4

PB5

GND

PB6

PB7

CNTL1

CNTL2

RESET

CNTLO

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AI02858

Table 2. Product Range

Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management

Unit (PMU), Automatic Power-down (APD)

2. SRAM may be backed up using an external battery.

Part Number

Primary Flash

Memory

Secondary NVM

SRAM

I/O Ports Voltage Range

Access Time

M8813F1Y

1 Mbit

256 Kbit EEPROM

16 Kbit

4.5-5.5 V

90 ns or

150 ns

M8813F2Y

1 Mbit

256 Kbit Flash memory

16 Kbit

M8834F2Y

2 Mbit

256 Kbit Flash memory

64 Kbit

M8813F1W

1 Mbit

256 Kbit EEPROM

16 Kbit

2.7-3.6 V

150 ns

M8813F2W

1 Mbit

256 Kbit Flash memory

16 Kbit

M8834F2W

2 Mbit

256 Kbit Flash memory

64 Kbit

Programmability (ISP) to Flash memory and
programmable logic. The result is a simple and
flexible

solution

for

embedded

designs.

FLASH+PSD devices combine many of the
peripheral

functions

found

MCU

based

applications. FLASH+PSD provides a glueless
interface

most

commonly-used

ROMless

MCUs.
Table 2 summarizes all the devices in the M88
Family.
The CPLD in the FLASH+PSD devices features
an optimized Macrocell logic architecture. The
Macrocell was created to address the unique
requirements of embedded system designs. It
allows direct connection between the system
address/data bus, and the internal FLASH+PSD

registers, to simplify communication between the
MCU and other supporting devices.
The FLASH+PSD device includes a JTAG Serial
Programming

interface,

allow

In-System

Programming (ISP) of the entire device. This
feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the
cost of field upgrades. Using ST's special Fast-
JTAG programming, a design can be rapidly
programmed into the FLASH+PSD.
The innovative FLASH+PSD family solves key
problems faced by designers when managing
discrete Flash memory devices, such as:
Complex address decoding
In-System (first-time) Programming (ISP)
Concurrent

EEPROM

Flash

memory

programming (IAP).

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M88 FAMILY

Figure 3. FLASH+PSD Block Diagram

PROG.

MCU

BUS

INTRF.

ADIO

PORT

CNTL0,

CNTL1,

CNTL2

AD0

AD15

CLKIN

(PD1)

CLKIN

PLD

INPUT

BUS

PROG.

PORT

PROG.

PORT

POWER

MANGMT

UNIT

MBIT

PRIMARY

FLASH

MEMORY

SECTORS

VSTDBY

PA0

PA7

PB0

PB7

PROG.

PORT

PROG.

PORT

PC0

PC7

PD0

PD2

ADDRESS/DATA/CONTROL

BUS

PORT

,
B

EXT

PORT

INPUT

MACROCELLS

PORT

,
B

256

KBIT

SECONDARY

EEPROM

FLASH

MEMORY

(BOOT

DATA)

SECTORS

KBIT

BATTERY

BACKUP

SRAM

RUNTIME

CONTROL

AND

I/O

REGISTERS

SRAM

SELECT

PERIP

I/O

MODE

SELECTS

MACROCELL

FEEDBACK

PORT

INPUT

CSIOP

FLASH

ISP

CPLD

(CPLD)

OUTPUT

MACROCELLS

FLASH

DECODE

PLD

( DPLD

)

PLD,

CONFIGURATION

FLASH

MEMORY

LOADER

JTAG

SERIAL

CHANNEL

( PC2

)

PAGE

REGISTER

EMBEDDED

ALGORITHM

SECTOR

SELECTS

SECTOR

SELECTS

GLOBAL

CONFIG.

SECURITY

AI02861D

Sometimes computers try to be too clever for their own good. Take this illustration for instance.
Just because so many of the labels are rotated through ninety degrees, FrameMaker seems to
want to insist on telling the postscript file that I would find it more convenient to see this page
displayed in landscape, rotated by ninety degrees. Well I wouldn't. So I am putting in all this text
just to weight the average in this direction.

M88 FAMILY

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The JTAG Serial Interface block allows In-System
Programming

(ISP).

Embedded

dual-bank

memories eliminates the need for an external Boot
EPROM

or Flash memory,

or an

external

programmer. To simplify Flash memory updates,
program execution is performed from a secondary
Flash memory (for the M88xxF2x) or EEPROM
(for the M8813F1x) while the primary Flash
memory is being updated. This solution avoids the
complicated hardware and software overhead
necessary to implement IAP.
ST makes available a software development tool,
PSDsoft, that generates ANSI-C compliant code
for use with your target MCU. This code allows you
to manipulate the non-volatile memory (NVM)
within the FLASH+PSD. Code examples are also
provided for:
Flash memory IAP via the UART of the host

MCU

Memory paging to execute code across several

FLASH+PSD memory pages

Loading,

reading,

and

manipulation

FLASH+PSD Macrocells by the MCU.

FLASH+PSD ARCHITECTURAL OVERVIEW
FLASH+PSD

devices

contain several

major

functional blocks. Figure 3 shows the architecture
of the M88 FLASH+PSD device family. The
functions of each block are described briefly in the
following sections. Many of the blocks perform
multiple functions and are user configurable.
Memory
The 1 or 2 Mbit (128K x 8, or 256K x 8) Flash
memory

the

primary

memory

the

FLASH+PSD. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary EEPROM or
Flash memory is divided into four equally-sized
sectors. Each sector is individually selectable.
The SRAM is intended for use as a scratch-pad
memory or as an extension to the MCU SRAM. If
an external battery is connected to Voltage Stand-
by (VSTBY, PC2), data is retained in the event of
power failure.
Each sector of memory can be located in a
different address space as defined by the user.
The access times for all memory types includes
the address latching and DPLD decoding time.
The M8813F1x has 64 bytes of OTP memory for
product identifiers, serial numbers, calibration
constants, etc..
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or

internal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different
memory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), each
optimized for a different function, as shown in
Table 3. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/
performance, and eases design entry.
The DPLD is used to decode addresses and to
generate

Sector

Select

signals

for

the

FLASH+PSD internal memory and registers. The
DPLD has 17 combinatorial outputs, which are
used to select memory sectors and JTAG. The
CPLD has 16 Output Macrocells (OMC) and 3
combinatorial outputs. The CPLD also has 24
Input Macrocells (IMC) that can be configured as
inputs to the PLDs. The PLDs receive their inputs
from the PLD Input Bus and are differentiated by
their output destinations, number of product terms,
and Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the MCU at run-time. There is a slight
penalty to PLD propagation time when invoking
the power management features.
I/O Ports
The FLASH+PSD has 27 individually configurable
I/O pins distributed over the four ports (Port A, B,
C, and D). Each I/O pin can be individually
configured for different functions. Ports can be
configured as standard MCU I/O ports, PLD I/O, or
latched

address

outputs

for

MCUs

using

multiplexed address/data buses. Ports A and B
can be configured to be open drain.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus or multiplexed
address/data bus for certain types of 8-bit MCUs.
MCU Bus Interface
FLASH+PSD interfaces easily with most 8-bit
MCUs that have either multiplexed or non-
multiplexed address/data buses. The device is
configured to respond to the MCU's control
signals, which are also used as inputs to the PLDs.
Where there is a requirement to use a 16-bit data
bus to interface to a 16-bit MCU, two PSDs must
be used. For examples, please see the full data
sheet.

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M88 FAMILY

JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial
interface allows complete programming of the
entire FLASH+PSD device. A blank device can be
completely programmed for the first time after it is
soldered to the board. The JTAG signals (TMS,
TCK,

TSTAT,

TERR,

TDI,

TDO)

can

multiplexed with other functions on Port C. Table 4
indicates the JTAG pin assignments. Four-pin
JTAG is also fully supported.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire
FLASH+PSD device can be programmed or
erased without the use of the MCU. The primary
Flash memory can also be programmed in-system
by

the

MCU

executing

the

programming

algorithms out of the secondary memory, or
SRAM.

The

secondary

memory

can

programmed the same way by executing out of the
primary Flash memory. The PLD

or other

FLASH+PSD

Configuration

blocks

can

programmed through the JTAG port or a device
insertion programmer. Table 5 indicates which
programming methods can program different
functional blocks of the FLASH+PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The FLASH+PSD also has some bits that are
configured at run-time by the MCU to reduce

power consumption of the CPLD. The Turbo bit in
the PMMR0 register can be reset to 0 and the
CPLD latches its outputs and goes to sleep until
the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the full data sheet for more details.

SECURITY AND NVM SECTOR PROTECTION
A security bit in the Protection Register enables
the software project, coded in the FLASH+PSD, to
be locked up. This bit is only accessible by the
system designer from the JTAG serial port, or from
a parallel insertion programmer. It cannot be
accessed from the MCU. The only way a security
bit can be cleared is to erase the entire chip.
The contents of the sectors of the primary and
secondary NVM blocks can be protected using bits
in the Protection Registers. These bits are
accessible from the MCU in the application code,
or

from

programmer

during

the

set-up

procedure.

Table 3. PLD I/O

Name

Inpu ts

Outp uts

Product

Terms

Decode PLD (DPLD)

Complex PLD (CPLD)

140

Table 4. JTAG SIgnals on Port C

Port C Pins

JTAG Signal

PC0

TMS

PC1

TCK

PC3

TSTAT

PC4

TERR

PC5

TDI

PC6

TDO

Table 5. Methods of Programming Different Functional Blocks of the FLASH+PSD

Functional Block

JTAG Programming

Device Programmer

IAP

Primary Flash Memory

Yes

Secondary EEPROM or Flash memory

Yes

PLD Array (DPLD and CPLD)

Yes

FLASH+PSD Configuration

Yes

OTP Row

Yes

Part Number M88