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April 2003
s
HIGH SPEED:
f
MAX
= 59MHz (TYP.) at V
CC
= 6V
s
LOW POWER DISSIPATION:
I
CC
= 4
µ
A(MAX.) at T
A
=25°C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN.) FOR QA to QH
|I
OH
| = I
OL
= 4mA (MIN.) FOR QH'
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 595
DESCRIPTION
The M74HC595 is an high speed CMOS 8-BIT
SHIFT
REGISTERS/OUTPUT
LATCHES
(3-STATE) fabricated with silicon gate
C
2
MOS
technology.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has 8 3-STATE
outputs. Separate clocks are provided for both the
shift register and the storage register.
The shift register has a direct-overriding clear,
serial input, and serial output (standard) pins for
cascading. Both the shift register and storage
register use positive-edge triggered clocks. If both
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC595
8 BIT SHIFT REGISTER
WITH OUTPUT LATCHES (3 STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC595B1R
SOP
M74HC595M1R
M74HC595RM13TR
TSSOP
M74HC595TTR
TSSOP
DIP
SOP
M74HC595
2/16
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X: Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 15
QA to QH
Data Outputs
9
QH'
Serial Data Outputs
10
SCLR
Shift Register Clear Input
11
SCK
Shift Register Clock Input
13
G
Output Enable Input
14
SI
Serial Data Input
12
RCK
Storage Register Clock
Input
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
SI
SCK
SCLR
RCK
G
X
X
X
X
H
QA THRU QH OUTPUTS DISABLE
X
X
X
X
L
QA THRU QH OUTPUTS ENABLE
X
X
L
X
X
SHIFT REGISTER IS CLEARED
L
H
X
X
FIRST STAGE OF S.R. BECOMES "L" OTHER
STAGES STORE THE DATA OF PREVIOUS
STAGE, RESPECTIVELY
H
H
X
X
FIRST STAGE OF S.R. BECOMES "H" OTHER
STAGES STORE THE DATA OF PREVIOUS
STAGE, RESPECTIVELY
X
H
X
X
STATE OF S.R. IS NOT CHANGED
X
X
X
X
S.R. DATA IS STORED INTO STORAGE
REGISTER
X
X
X
X
STORAGE REGISTER STATE IS NOT CHANGED
M74HC595
3/16
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
M74HC595
4/16
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) Power dissipation at 65°C. Derating from 65
°
C to 125
°
C: DIP Package -10mW/°C; SO Package -7mW/°C; TSSOP Package -6.1mW/°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
±
20
mA
I
OK
DC Output Diode Current
±
20
mA
I
O
DC Output Current
±
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
±
70
mA
P
D
Power Dissipation
DIP
750(*)
mW
SOP
500(*)
mW
TSSOP
450(*)
mW
T
stg
Storage Temperature
-65 to +150
°C
T
L
Lead Temperature (10 sec)
300
°C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
°C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2.0V
0 to 1000
ns
V
CC
= 4.5V
0 to 500
ns
V
CC
= 6.0V
0 to 400
ns
M74HC595
5/16
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level Output
Voltage
(for QH' outputs)
2.0
I
O
=-20
µ
A
1.9
2.0
1.9
1.9
V
4.5
I
O
=-20
µ
A
4.4
4.5
4.4
4.4
6.0
I
O
=-20
µ
A
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-7.8 mA
5.68
5.8
5.63
5.60
V
OH
High Level Output
Voltage
(for QA to QH
outputs)
2.0
I
O
=-20
µ
A
1.9
2.0
1.9
1.9
V
4.5
I
O
=-20
µ
A
4.4
4.5
4.4
4.4
6.0
I
O
=-20
µ
A
5.9
6.0
5.9
5.9
4.5
I
O
=-6.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-7.8 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
(for QH' outputs)
2.0
I
O
=20
µ
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=20
µ
A
0.0
0.1
0.1
0.1
6.0
I
O
=20
µ
A
0.0
0.1
0.1
0.1
4.5
I
O
=4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
=7.8 mA
0.18
0.26
0.33
0.40
V
OL
Low Level Output
Voltage
(for QA to QH
outputs)
2.0
I
O
=20
µ
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=20
µ
A
0.0
0.1
0.1
0.1
6.0
I
O
=20
µ
A
0.0
0.1
0.1
0.1
4.5
I
O
=6.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
=7.8 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
±
0.1
±
1
±
1
µ
A
I
OZ
High Impedance
Output Leakage
Current
6.0
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
±
0.5
±
5
±
10
µ
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
µ
A
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