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L9826

October 2002

OUTPUTS CURRENT CAPABILITY UP TO
500mA, R

2.2

AT T

= 25°C

PARALLEL CONTROL INPUTS FOR
OUTPUTS 1 AND 2

SPI CONTROL FOR OUTPUTS 1 TO 8

RESET FUNCTION WITH RESET SIGNAL AT
NRES PIN OR UNDERVOLTAGE AT V

- INTRINSIC OUTPUT VOLTAGE CLAMPING
AT TYP. 50V

OVERCURRENT SHUTDOWN AT OUTPUTS
3 TO 8

SHORT CIRCUIT CURRENT LIMITATION
AND SELECTIVE THERMAL SHUTDOWN AT
OUTPUTS 1 AND 2

OUTPUT STATUS DATA AVAILABLE ON THE SPI

DESCRIPTION

The L9826 is a Octal Low-Side Driver Circuit, dedicated
for automotive applications. Output voltage clamping is
provided for flyback current recirculation, when induc-
tive loads are driven. Chip Select and Serial Peripheral
Interface for outputs control and diagnostic data trans-
fer. Parallel Control inputs for two outputs.

SO20 (16+2+2)

ORDERING NUMBER: L9826

Octal Low-Side Driver for resistive and inductive loads with

serial/parallel input control, output protection and diagnostic

BLOCK DIAGRAM

NCS

SDI

CLK

SDO

NON1

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

GND

Diag1

Diag8

nRES

CH1

Diag1

CH7

Diag7

CH3

Diag3

CH4

CH5

CH6

CH2

NON2

Diag2

Diag4

Diag5

Diag6

CH8

Diag8

Fault Latch

Reset

i
ft R

t
er

tpu

t
La

SPI

t
e

r
f
a

Latch / Driver

Reset

Undervoltage

RESET

Latch / Driver

Q2
Q3
Q4
Q5
Q6
Q7

Diag2
Diag3
Diag4
Diag5
Diag6
Diag7

VCC

VDG

IOL

VDG

Overtemperature Detection

L9826

2/12

PIN FUNCTION

PIN CONNECTIONS (Top view)

N°

Pin

Description

Out 6

output 6

Out 1

output 1

nRes

asynchronous nRes

NCS

chip select (active low)

GND

device ground

GND

device ground

NON1

control input 1

SDO

serial data output

Out 8

output 8

Out 3

output 3

Out 5

output 5

Out 2

output 2

SDI

serial data input

CLK

serial clock

GND

device ground

GND

device ground

NON2

control input 2

supply voltage

Out 7

output 7

Out 4

output 4

OUT6

OUT1

nRES

NCS

GND

NON1

GND

SDO

OUT8

OUT2

SDI

CLK

GND

NON2

Vcc

OUT7

OUT4

OUT3

OUT5

PINCON_L9826

3/12

L9826

ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device

Notes: 1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E £

0,2mJ.

2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.

For currents determined within the device:

3. When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may

occur.

THERMAL DATA

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply voltage

-0.3

Inputs and data lines
(NONx, NCS, CLK, SDI, nRes)

Voltage
(NONx, NCS, CLK, SDI, nRes)

-0.3

Protection diodes current

1ms

-20

Outputs (Out1 ... Out8)

OUTc

Continuous output voltage

-1,0

OUT

Output current

-2

1,0

OUTcl

Output clamp energy

OUT

250mA

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Outputs (Out1 ... Out8)

OUT

Output current (Out1 ... Out8)

1,0

i = 1-8

Total average-current all outputs

2.0

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Thermal shutdown

JSC

Thermal shutdown threshold

150

165

°C

Thermal resistance

thjA-one

Single output (junction ambient)

°C/W

thjA-all

All outputs (junction ambient)

°C/W

thj-pin

Junction to Pin

°C/W

O UT i

L9826

4/12

ELECTRICAL CHARACTERISTCS (4.5V

5,5V; -40°C

150°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply voltage

ccSTB

Standby current

without load (nRes = Low)

µA

ccOPM

Operating mode

OUT1 ... 8

= 500mA

SPI - CLK = 3MHz
NCS = LOW
SDO no load

during reverse output

current

out

= -2A

100

Inputs (NONx. NCS, CLK, SDI, nRes)

INL

Low level

-0.3

0.2·V

INH

High level

0.7·V

+0,3

hyst

Hysteresis voltage

0.85

Input current

= V

-10

µA

Pullup resistance
(NONx, NCS, CLK, SDI)
Pulldown resistance (nRes)

250

Input capacitance

Serial data outputs

SDOH

High output level

SDO

= -4mA

-0.4

SDOL

Low output level

SDO

= 3,2mA

0.4

SDOL

Tristate leakage current

NCS = high; 0V

SDO

-10

µA

SDO

Output capacitance

SDO

= 300kHz

Outputs OUT 1 ... 8

OUTL1 - 8

Leakage current

OUTx = OFF; V

OUTx

= 25V;

= 5V

100

µA

OUTL1 - 8

Leakage current

OUTx = OFF; V

OUTx

= 16V;

= 5V

100

µA

OUTL1 - 8

Leakage current

OUTx = OFF; V

OUTx

= 16V;

= 1V

µA

clp

Output clamp voltage

1mA

clp

outp

; I

test

= 10mA with

correlation

DSon

On resistance OUT 1 ... 8

OUT

= 500mA; T

= +150°C

3.0

OUT

Output capacitance

OUT

= 16V; f = 1MHz

300

5/12

L9826

Outputs short circuit protection

SBC

Overcurrent shutoff threshold

OUT3 ... OUT8

0.45

1.1

LIM

Short circuit current limitation

OUT1; OUT2

0.5

1,0

SCB

Delay shutdown

for output 3 ... 8; I

OUT

1/2 I

SCB

0.2

3,0

µs

Diagnostics

Diagnostic threshold voltage

0.32·V

0.4·V

Open load detection sink
current

out

= V

100

µA

Diagnostic detection filter time
for output 1 & 2 on each
diagnostic condition

µs

Outputs timing

don1

Turn ON delay of OUT 1 and 2

NON

1, 2

= 50% to V

OUT

= 0,9·V

bat

NCS = 50% to V

OUT

= 0,9·V

bat

µs

don2

Turn ON delay of OUT 3 to 8

NCS = 50% to V

OUT

= 0,9·V

bat

µs

doff

Turn OFF delay of OUT 1 to 8

NCS = 50% to V

OUT

= 0,1·V

bat

NON

1, 2

= 50% to V

OUT

= 0,1·V

bat

µs

on1/dt

Turn ON voltage slew-rate

For output 3 to 8; 90% to 30% of
V

bat

; R

= 500

; V

bat

= 16V

0.7

3.5

V/µs

on2/dt

Turn ON voltage slew-rate

For output 1 and 2; 90% to 30% of
V

bat

; R

= 500

; V

bat

= 16V

V/µs

off1/dt

Turn OFF voltage slew-rate

For output 1 to 8; 30% to 90% of
V

bat

; R

= 500

; V

bat

= 16V

V/µs

off2/dt

Turn OFF voltage slew-rate

For output 1 to 8; 30% to 80% of
V

bat

; R

= 500

; V

bat

= 0.9 · V

clp

V/µs

Serial diagnostic link (Load capacitor at SDO = 100pF)

clk

Clock frequency

50% duty cycle

MHz

clh

Minimum time CLK = HIGH

160

cll

Minimum time CLK = LOW

160

pcld

Propagation delay
CLK to data at SDO valid

4,9V

5,1V

100

csdv

NCS = LOW to data at SDO
active

100

sclch

CLK low before NCS low

Setup time CLK to NCS change H/L

100

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

ELECTRICAL CHARACTERISTCS (continued)

L9826

6/12

FUNCTIONAL DESCRIPTION

General

The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using
the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power
outputs features voltage clamping function for flyback current recirculation and are protected against short cir-
cuit to Vbat.

The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and ther-
mal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition
for all outputs. The outputs status can be read out via the serial interface.

The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes
signal.

Output Stages Control

Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1
and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These
inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.

The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.

The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every
falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.

hclcl

CLK change L/H after NCS =
low

100

scld

SDI input setup time

CLK change H/L after SDI data
valid

hcld

SDI input hold time

SDI data hold after CLK change H/L

sclcl

CLK low before NCS high

150

hclch

CLK high after NCS high

150

pchdz

NCS L/H to output data float

100

NCS pulse filter time

Multiple of 8 CLK cycles inside
NCS period

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

ELECTRICAL CHARACTERISTCS (continued)

7/12

L9826

Figure 1. Timing of the Serial Interface.

The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and
the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since
the last NCS falling edge. The NCS changes only at low CLK.

Outputs Control Tables :

Figure 2. Output Control register structure

Outputs 1, 2:

Outputs 3 to 8:

NON1, 2

SPI-bit 1, 2

SPI-bit 3 ... 8

Output 1, 2

off

Output 3 ... 8

off

NCS

CLK

SDI

SDO

tsclch

thclcl

tclh

tcll

tsclcl

thclch

tcsdv

tpcld

tpchdz

not defined

tscld

thcld

MSB

LSB

Control-bit output 7

Control-bit output 5

Control-bit output 3

Control-bit output 1

Control-bit output 8

Control-bit output 6

Control-bit output 4

Control-bit output 2

L9826

8/12

Power outputs characteristics

for flyback current, outputs short circuit protection and diagnostics

For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V.
This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is
absorbed in the chip.

Output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current): when the output
current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is
switched off immediately.

Output short circuit protection for outputs 1 and 2 (dedicated for loads with inrush current, as lamps): when the
load current would exceed the short circuit limit value, the corresponding output goes in a current regulation
mode. The output current is determined by the output characteristics and the output voltage depends on the
load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rap-
idly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set
and the corresponding output switched off.

For the load diagnostic in output off condition each output features a diagnostic current sink, typ 60µA.

Diagnostics

The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 · V

Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and latched. The fault latch-
es are cleared during NCS low. The latch stores the status bit, so the first reading after the error occurred might
be wrong. The second reading is right.

Diagnostic Table for outputs 1 and 2 in parallel controlled mode:

Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output ex-
ceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due
to thermal shutdown. The status bit is low.

Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the
output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-
rent source, the load is interrupted. The diagnostic bit is low.

For outputs 3 to 8 the output status signals, are fed directly to the SPI register.

Diagnostic Table for outputs 1 to 8 in SPI controlled mode:

Output 1, 2

Output-voltage

Status-bit

Output-mode

off

> DG-threshold

high

correct operation

off

< DG-threshold

low

fault condition 2)

< DG-threshold

high

correct operation

> DG-threshold

low

fault condition 1)

Output 1 ... 8

Output-voltage

Status-bit

Output-mode

off

> DG-threshold

high

correct operation

off

< DG-threshold

low

fault condition 2)

< DG-threshold

low

correct operation

> DG-threshold

high

fault condition 1)

9/12

L9826

The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output
exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has
been switched off. The diagnostic bit is high.

Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and 2.

At the falling edge of NCS the output status data are transferred to the shift register. When NSC is low, data bits
contained in the shift register are transferred to SDO output et every rising CLK edge.

Figure 3. The Pulse Diagram to Read the Outputs Status Register

Figure 4. The Structure of the Outputs Status Register

NCS

CLK

SDI

SDO

MSB

LSB

MSB

LSB

Diag2 Diag4 Diag6 Diag8 Diag1 Diag3 Diag5 Diag7

MSB

LSB

Diagnostic-bit output 7

Diagnostic-bit output 5

Diagnostic-bit output 3

Diagnostic-bit output 1

Diagnostic-bit output 8

Diagnostic-bit output 6

Diagnostic-bit output 4

Diagnostic-bit output 2

L9826

10/12

APPLICATION INFORMATION

The typical application diagram is shown in Fig. 5.

Figure 5. Typical Application Circuit Diagram for the L9826 Circuit.

For higher current driving capability two outputs of the same kind can be paralleled. In this case the maximum
flyback energy should not exceed the limit value for single output.

The immunity of the circuit with respect to the transients at the output is verified during the characterization for
Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with
200pF series capacitor. All outputs withstand testpulses without damage.

The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characteriza-
tion for the typical application with R = 30

to 100

, L= 0 to 600mH loads. The Test Pulses are coupled to the

outputs with 200pF series capacitor.

LOC

NRE

BAT

R, L loads

µP

L9826

VOLTAGE

REGULATOR

NCS

S DI

CLK

SDO

NON1

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

GND

Diag1

Diag8

nRES

CH1

Diag1

CH7

Diag7

CH3

Diag3

CH4

CH5

CH6

CH2

NON2

Diag2

Diag4

Diag5

Diag6

CH8

Diag8

Fault Latch

Reset

t
R

i
st

t
put

t
e

r
f
ace

Latch / Driver

Reset

Undervoltage

RE SET

Latch / Driver

Q2
Q3
Q4
Q5
Q6
Q7

Diag2
Diag3

Diag4
Diag5
Diag6
Diag7

VCC

VDG

IOL

VDG

Overtemperature Detection

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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12/12

L9826

Part Number L9826