VGA/SVGA/XGA 24bit Receiver
Description
CXB1454R is the 1 chip deserializer for VGA/SVGA/
XGA 24bit color digital RGB, and meet to the Gigabit
Video Interface specification.
Features
· 1 chip receiver for serial transmission of 24-bit color
VGA/SVGA/XGA picture
· On chip cable equalizer circuit to compensate the
cable loss
· On chip PLL circuit for data and clock recovery
· On chip panel mode automatically selectable circuit
· TTL compatible I/O
· Support 1 pixel/shiftclock mode with 1 chip and 2
pixel/shiftclock mode with 2 chips
· +3.3V single power supply
· Low power consumption
· 64pin plastic LQFP package with body size 14mm
×
14mm
Structure
Bipolar silicon monolithic IC
Block Digagram & Pin out
Absolute Maximum Ratings
· Supply voltage
Vcc
4.0
V
· Storage temperature
Tstg
65 to +150
°C
· Allowable power dissipation
P
D
1710
mW
Recommended Operating Condition
· Supply voltage
Vcc
3.3 ± 0.16
V
· Operating temperature Topr
0 to +60
°C
1
E98X24B03
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXB1454R
64 pin LQFP (Plastic)
10 11
1
Decoder
CDR
PLL
Serial
to
Parallel
Converter
12 13 14 15 16
2
3
4
5
6
7
8
9
63
64
61
62
40 39 38 37 36 35 34 33
48
41
42
43
44
45
46
47
Cable
EQ
60
59
58
57
56
55
54
53
52
51
50
49
21
30
31
32
22
23
24
25
26
27
28
29
17
18
19
20
CLKPOL
R0
R1
V
EE
T
VccT
V
EE
G
VccG
R2
R3
R4
R5
V
EE
G
V
CC
G
R6
R7
V
EE
T
CNTL
DE
SFTCLK
V
EE
T
VccT
V
EE
G
VccG
HSYNC
VSYNC
B7
B6
V
EE
G
VccG
B5
B4
VccT
LPFB
LPFA
V
EE
S
V
EE
A
VccA
TESTEXN
REFRQN
SDATAN
SDATAP
REFRQP
TESTSB
TESTDT
LOS
PANEL1
PANEL0
REXT
V
EE
T
B3
B2
B1
B0
G7
G6
VccT
V
EE
T
G5
G4
G3
G2
G1
G0
VccT
Fig. 1. Block Diagram & Pin out
2
CXB1454R
Pin List
Tab. 1. Power/Ground
Pin Name
V
CC
T
V
EE
T
V
CC
G
V
EE
G
V
CC
A
V
EE
A
V
EE
S
8, 16, 28, 53, 64
1, 9, 17, 29, 52
20, 26, 55, 61
21, 27, 54, 60
44
45
46
TTL power surpply, should be connected to 3.3V ± 5%
TTL ground, connected to 0V
Logical core power surpply, connected to 3.3V ± 5%
Logical core ground, connected to 0V
Analog power surpply, connected to 3.3V ± 5%
Analog ground, connected to 0V
Analog substrate, connected to 0V
Pin Number
Descriptions
3
CXB1454R
Tab. 2. Digital Signals
Pin Name
SFTCLK
RED (7 to 0)
GRN (7 to 0)
BLU (7 to 0)
HSYNC
VSYNC
CNTL
DE
LOS
PANEL (1, 0)
CLKPOL
TESTEXN
TESTDT
TESTSB
51
18, 19, 22, 23,
24, 25, 30, 31,
6, 7, 10, 11,
12, 13, 14, 15,
58, 59, 62, 63,
2, 3, 4, 5
56
57
49
50
36
35, 34
32
43,
37,
38
TTL out
TTL out
TTL out
TTL out
TTL out
TTL out
TTL out
TTL in
TTL in
TTL in
Shift clock, for the data
fetch at falling or rising
edge
Pixel data
Hsync data
Vsync data
Control data
Display enable data
Los of signal
Panel mode select switch
Trigger edge select switch
Reserved for TEST under
fabrication
Pin Number
Type
Descriptions
Equivalent circuit
V
CC
T
TTL-OUT
V
EE
T
300
6k
6k
V
CC
T
TTL-IN
V
EE
T
V
CC
G
V
EE
G
V
CC
G
SDATAP/N
REFRQP/N
V
EE
G
SDATAP/N
REFRQP/N
40, 41
39, 42
Rx
Rx
Serial input
Refclk request
4
CXB1454R
Tab. 3. Special
Pin Name
33
External Resister
Pin Number
Descriptions
Equivalent circuit
REXT
47, 48
External loop filter
LPFA/B
V
CC
G
REXT
V
EE
G
V
CC
A
LPFA
LPFB
V
EE
A
5
CXB1454R
Electrical characteristics
Tab. 4. Absolute Maximum Rating
Description
Power supply voltage
TTL DC input voltage
TTL output current (High)
TTL output current (Low)
Serial input pin voltage
REFRQ output pin voltage
Storage temperature
V
CC
V
I
_T
I
OH
_T
I
OL
_T
Vsdin
V
RQ
out
Tstg
0.3
0.5
20
0
0.5
0.5
65
4
5.5
0
20
V
CC
+ 0.5
V
CC
+ 0.5
150
V
V
mA
'
mA
V
V
°C
Symbol
Min.
Typ.
Max.
Unit
Comments
Tab. 5. Recommended Operating Conditions
Description
Power supply voltage (Include V
CC
T5)
Operating temperature
V
CC
Topr
3.135
0
3.3
3.465
60
V
°C
Symbol
Min.
Typ.
Max.
Unit
Comments
Tab. 6. DC Characteristics (Under the recommended conditons. See Tab. 5)
Description
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Output HIGH current (REFRQ)
Output LOW current (REFRQ)
Input dynamic range (SDATA)
Input dynamic range (SDATA)
Supply current
V
IH
_T
V
IL
_T
I
IH
_T
I
IL
_T
V
OH
_T
V
OL
_T
I
OH
_RQ
I
OL
_RQ
V
IM
_SD
V
ID
_SD
I
CC
2
0
400
2.25
0.1
7.8
V
CC
0.4
0.5
0
325
350
5.5
0.8
20
0.5
+0.1
11
V
CC
+ 0.2
+0.5
440
465
V
V
µA
µA
V
V
mA
mA
V
V
mA
mA
V
IN
= V
CC
V
IN
= 0
I
OH
= 0.2mA
I
OL
= 4mA
See Fig. 3, 4
REXT = 1.3k
Common mode voltage
Differential voltage
65MHz,
All low pattern,
Outputs open
65MHz,
Worst case pattern
See Fig. 8
Outputs open
Symbol
Min.
Typ.
Max.
Unit
Conditions
6
CXB1454R
V
CC
A/G/T
V
EE
A/G/T
V
CC
CXB1454R
A
A
37
38
43
39
42
TESTDT
TESTSB
TESTEXN
REFRQP
REFRQN
150
150
50
50
Fig. 2. I
OH
_RQ and I
OL
_RQ DC measurement
Tab. 7. AC Characteristics (Under the recommended conditons. See Tab. 5)
Description
Minimum SFTCLK frequency
Maximum SFTCLK frequency
SFTCLK duty factor
Pixel/Sync/Cntl/DE setup to
SFTCLK
Pixel/Sync/Cntl/DE hold to
SFTCLK
SFTCLK rise time
SFTCLK fall time
Pixel/Sync/Cntl/DE rise time
Pixel/Sync/Cntl/DE fall time
CLOCK mode assert time
CLOCK mode deassert time
LOS signal assert time
LOS signal deassert time
Fsftclk
Dsftclk
Tsetup
Thold
Torc
Tofc
Tofd
Tord
TAclk
TDclk
TAlos
TDlos
65.0
40
16
10
5
17
11
6
0.9
50
0.5
0.1
25.0
60
3
2.5
4.5
2
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Vth = 1.4V, C
L
= 10pF
Vth = 1.4V, C
L
= 10pF
25MHz
40MHz
65MHz
Vth = 1.4V, C
L
= 10pF
25MHz
40MHz
65MHz
0.8 to 2.0V, C
L
= 10pF
2.0 to 0.8V, C
L
= 10pF
0.8 to 2.0V, C
L
= 10pF
2.0 to 0.8V, C
L
= 10pF
Symbol
Min.
Typ.
Max.
Unit
Conditions
TESTDT
TESTSB
TESTEXN
Fig. 3. I
OH
_RQ and I
OL
_RQ DC measurement setting
Electrical characteristics
7
CXB1454R
Timing Chart
Tofc
Setup/hold time is refered from
rising edge in CLKPOL = GND
falling edge in CLKPOL = Vcc or OPEN
Torc
Vth
1/Fsftclk
2.0V
0.8V
SFTCLK
REDxx
GRNxx
BLUxx
H/Vsync
CNTL
DE
Thold
Tsetup
2.0V
0.8V
Tofd
Tord
Dsftclk/Fsftclk
Fig. 6. Refclk request timing
SDATAP
SDATAN
Pixel
Sync/Cntl/DE
TAclk
error
TDclk
REFRQP
REFRQN
SftClk
Indeterminate
Indeterminate
V
CC
A/G/T
V
EE
A/G/T
V
CC
CXB1454R
Cprobe
oscillo-
scope
CL'
CL' + Cprobe = 10pF
TTLout
Fig. 4. Pixel/Sync/Cntl/DE waveform measurement
Fig. 5. TTL output timing
8
CXB1454R
Fig. 7. Idle mode timing
LOS
SDATAP
SDATAN
TDlos
TAlos
NRZ data
Fig. 8. Worst case test pattern
SFTCLK
RGB
<7, 5, 3, 1>
RGB
<6, 4, 2, 0>
T
T
f
f/2
f/2
9
CXB1454R
CLKPOL Pin Control
The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.)
The CLKPOL pin is open High TTL input.
Table 8. SFTCLK Polarity
PANEL1
L
L
H
H
L
H
L
H
VGA (640
×
480)
SVGA (800
×
600)
XGA (1024
×
768)
VGA to XGA
PANEL0
Supporting panel size
25MHz
40MHz
65MHz
25MHz to 65MHz
Shift clock
750Mbps
1200Mbps
1950Mbps
750Mbps to 1950Mbps
Serial rate
CLKPOL
L
H
Rising edge
Falling edge
Receiver operation trigger
Table 9. Panel Mode
LOS Pin Output
The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is
disconnected or the transmitter is idle.
The LOS pin is TTL output.
Table 10. Test Mode
TESTEXN
L
H
X
H
TESTDT
X
H
TESTSB
Test mode
Normal mode
Operation mode
PANEL1 and 0 Pin Control
The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.)
For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1
and 0 to High.
The PANEL1 and 0 pins are open High TTL inputs.
Test Pin Control
The TESTEXN, TESTDT and TESTSB pins are for test only. Select normal mode. (See Table 10.)
The TESTEXN, TESTDT and TESTSB pins are open High, TTL inputs.
10
CXB1454R
Applications
CXB1454R GVIF receiver is applied to the digital RGB signal transmission for
P/C with LCD monitor
Video on demand system
Monitoring system
Graphical controller
Projector
Digital TV monitor
Car navigation system
with GVIF transmitter, CXB1455R.
CXB1455R GVIF Transmitter
STP or Twin axial
CXB1454R GVIF Receiver
RED (7 to 0)
GRN (7 to 0)
BLU (7 to 0)
SYNC/CNTL/DE
SHIFTCLOCK
8
8
8
4
PLL
Serial
to
Parallel
Converter
Cable
Equalizer
D
e
c
o
d
e
r
8
8
8
4
E
n
c
o
d
e
r
Parallel
to
Serial
Converter
Cable
Driver
PLL
RED (7 to 0)
GRN (7 to 0)
BLU (7 to 0)
SYNC/CNTL/DE
SHIFTCLOCK
Fig. 9. Block Diagram of GVIF transceiver chip set
11
CXB1454R
(1) CHIP RESISTOR (1%)
(2) CHIP CAPACITOR
(3) FORMED BY THE PRINTED CIRCUIT PATTERN
(L = 0.5 to 1.0mm / W = 0.5 to 1.0mm)
470 (1)
100p (2)
0.1 to 0.4n (3)
0.1 to 0.4n (3)
V
CC
0.1 to 0.4n
(3)
E
E
0.1µ
(2)
5
4
3
2
1
0
MSB
LSB
GREEN DATA
0.1µ (2)
E
0.1µ
(2)
Differential cable
Connector
33µ
16V
47p
(2)
1
0
0
(
1
)
150
(1)
150
(1)
470 (1)
10 11
1
12 13 14 15 16
2
3
4
5
6
7
8
9
63
64
61
62
40 39 38 37 36 35 34 33
48
41
42
43
44
45
46
47
60
59
58
57
56
55
54
53
52
51
50
49
21
30
31
32
22
23
24
25
26
27
28
29
17
18
19
20
CLKPOL
R0
R1
V
EE
T
VccT
V
EE
G
VccG
R2
R3
R4
R5
V
EE
G
V
CC
G
R6
R7
V
EE
T
CNTL
DE
SFTCLK
V
EE
T
VccT
V
EE
G
VccG
HSYNC
VSYNC
B7
B6
V
EE
G
VccG
B5
B4
VccT
L
P
F
B
L
P
F
A
V
E
E
S
V
E
E
A
V
c
c
A
T
E
S
T
E
X
N
R
E
F
R
Q
N
S
D
A
T
A
N
S
D
A
T
A
P
R
E
F
R
Q
P
T
E
S
T
S
B
T
E
S
T
D
T
L
O
S
P
A
N
E
L
1
P
A
N
E
L
0
R
E
X
T
V
E
E
T
B
3
B
2
B
1
B
0
G
7
G
6
V
c
c
T
V
E
E
T
G
5
G
4
G
3
G
2
G
1
G
0
V
c
c
T
Vcc
7
6
Vcc
0.1µ (2)
5
4
3
2
1
0
MSB
LSB
BLUE DATA
7
6
D
E
E
0.1µ
(2)
Vcc
V
S
Y
N
C
H
S
Y
N
C
S
F
T
C
L
K
C
N
T
L
0.1µ
(2)
3
3
0
47p
(2)
E
V
c
c
0.1µ
(2)
1.3k
(1)
330
Vcc
SW1
330
H: FALLING EDGE TRIGGER
L: RISING EDGE TRIGGER
5
4
3
2
1
0
MSB
LSB
RED DATA
7
6
Vcc
0.1µ (2)
Fig. 10. Recommended application circuit
Application Cicuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
12
CXB1454R
Recommended Printed Circuit Board Structure
L1: Cu plate (18µm) + solder coat
L2: Cu plate (36µm)
I1: Fiber-glass epoxy core (0.3mm)
I2: Fiber-glass epoxy core (0.8mm)
L3: Cu plate (36µm)
I3: Fiber-glass epoxy core (0.3mm)
L4: Cu plate (18µm) + solder coat
Recommended Printed Circuit Board Pattern
POWER and special signal routing example
17
G
G
L2 doesn't have plane
in this area
0.5mm
Through hole to the GND plane (L2)
Through hole to the V
CC
E/V
CC
G plane (L3)
Through hole to the V
CC
T plane (L3)
Chip capacitor
Chip resistor
E
T
G
FET
T
T
T
T
T
T
T
T
G
E
G
E
T
T
G
E
G
G
G
T
G
E
16
1
32
49
64
48
33
G
L
P
F
B
L
P
F
A
V
E
E
S
V
E
E
A
V
c
c
A
T
E
S
T
E
X
N
R
E
F
R
Q
N
S
D
A
T
A
N
S
D
A
T
A
P
R
E
F
R
Q
P
T
E
S
T
S
B
T
E
S
T
D
T
L
O
S
P
A
N
E
L
1
P
A
N
E
L
0
R
E
X
T
V
E
E
T
B
3
B
2
B
1
B
0
G
7
G
6
V
c
c
T
V
E
E
T
G
5
G
4
G
3
G
2
G
1
G
0
V
c
c
T
CLKPOL
R0
R1
V
EE
T
VccT
V
EE
G
VccG
R2
R3
R4
R5
V
EE
G
VccG
R6
R7
V
EE
T
CNTL
DE
SFTCLK
V
EE
T
VccT
V
EE
G
VccG
HSYNC
VSYNC
B7
B6
V
EE
G
VccG
B5
B4
VccT
6mm
Fig. 11. Recommended Printed Circuit Board Structure
Fig. 12. Recommended Printed Circuit Board Pattern
13
CXB1454R
Micro Strip Line
For maximum performance, the impedance between the pins SDDATAP/N of the LSI and the footprint of the
connector should be 50
using a micro strip line. 50
impedance can be reached when using 0.5mm width
pattern lines on L1 using this circuit board structure. The length of the lines should be identical and through-
hole should not be used. L2 is recommended as the large ground plane.
Terminators
Terminators (100
resistor) should be located as close to the LSI as possible.
Filter Devices and Reference Registors
Capacitors and resistors which are connected to LPFA/B and REXT are filters and reference resistors. The
region of Layer 2 (L2) is under the device and conductive patterns. The ground plane should be taken off in
order to reduce parasitic capacitors.
Bypass Capacitors
Bypass capacitors (0.1µF SMD type) should be located as close to the pins as possible. Refer to the
recommendation.
14
CXB1454R
Recommendation for Cable and Connector Characteristics
The GVIF system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small
amplitude differential signal. In order to solve the problems of high speed data transmission such as signal
reflection, reduce the signal level and EMI. In order to achieve the best solution, note the following:
Rx
termination
100
Rx
LSI
Tx
LSI
Tx
termination
50
Microstrip
line
(50
)
Foot
print
Connector
Cable
(diff. 100
)
Connector
Foot
print
Microstrip
line
(50
)
It is important to note the following issues for a good data transmission system:
· Good impedance matching
Differential impedance should be fit to the recommended template on the next page.
· Cable loss should be small and the loss curve should be smooth.
Maximum loss should be less than 15dB at 1GHz for the CXB1454R which has a built-in cable equalizer.
See the next page.
· Skew of POS/NEG (differential signal) should be small
Less than 12% of 1-bit time or 160ps@VGA, 100ps@SVGA, 60ps@XGA.
· Good EMI performance cable and connectors.
In order to satisfy these issues, the recommendations are as follows:
· Use the differential cable which provides good controlled impedance, low loss and good skew matching.
A shielded twisted pair (STP) cable is recommended.
· Use a low reflectance connector.
· To minimize interference from other signals, high speed signal lengths should be identical.
· Use double shielded cable.
15
CXB1454R
150
110
106
94
90
75
Zo
(
)
< 500ps
< 500ps
Microstrip
line
Foot
print
Connector
Connector
Foot
print
Microstrip
line
Loss
Frequency
< 15dB
1GHz
2dB
Fitting curve
Measured curve
Recommended Transmission Path : Differential impedance template
Recommended Transmission Path : Attennation Characteristics
16
CXB1454R
T
1.00V/div
1.00V/div
5ns/div
TTL output waveform with C
L
= 10pF
SFTCLK
65MHz
TTL output
B0
65Mb/s
TTL output
ATTEN 40dB
RL 119.2dBµV
10dB/
D
R
C
CENTER 65.000MHz
RBW 100kHz
VBW 100kHz
SPAN 9.900MHz
SWP 50.0ms
SFTCLK Power spectrum
17
CXB1454R
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PALLADIUM PLATING
COPPER ALLOY
PACKAGE STRUCTURE
LQFP-64P-L02
LQFP064-P-1414
0.7g
0.37 0.07
+ 0.08
(0.35)
(
0
.
1
2
5
)
0
.
1
4
5
±
0
.
0
4
64PIN LQFP (PLASTIC)
0.8
14.0 ± 0.1
16.0 ± 0.2
48
33
49
32
17
16
1
64
0.37 0.07
+ 0.08
A
B
(
0
.
5
)
(
1
5
.
0
)
1.7MAX
0.1
0.13 M
0.1 ± 0.1
0.25
(
0
.
5
)
0
.
6
±
0
.
2
0° to 10°
DETAIL A
DETAIL B
NOTE: Dimension "
" does not include mold protrusion.
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
Sony Corporation
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