VGA/SVGA/XGA digital data serial receiver
Features
· 1 chip receiver for serial transmission of 18bit color
VGA/SVGA/XGA picture
· On chip differential cable driver
· TTL/CMOS compatible interface
· Support 1 pixel/shiftclock mode & 2 pixel/shiftclock
mode
· +3.3V single power supply
· Low power consumption
· 80pin Plastic QFP Package
(Body size: 14mm
×
14mm)
Block Digagram & Pin out
1
E97937-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXB1452Q
80 pin QFP (Plastic)
V
EE
T
BLU1 (3)
BLU1 (2)
BLU1 (1)
BLU1 (0)
GRN1 (5)
GRN1 (4)
GRN1 (3)
GRN1 (2)
V
CC
T
V
EE
T
GRN1 (1)
GRN1 (0)
RED1 (5)
RED1 (4)
RED1 (3)
RED1 (2)
RED1 (1)
RED1 (0)
V
CC
T
LPFB
LPFA
V
EE
S
V
EE
A
V
CC
A
TESTSB
REFRQN
SDATAN
SDATAP
REFRQP
LOS
V
EE
T
V
CC
T
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
V
EE
T
V
CC
T
BLU0 (0)
BLU0 (1)
BLU0 (2)
V
EE
G
V
CC
G
BLU0 (3)
BLU0 (4)
BLU0 (5)
V
EE
T
V
CC
T
GRN0 (0)
GRN0 (1)
GRN0 (2)
GRN0 (3)
GRN0 (4)
GRN0 (5)
V
EE
G
V
CC
G
V
EE
T
V
EE
G
TESTDT
PANEL1
PANEL0
CKMODE
CNTL3
CNTL2
CNTL1
V
CC
G
V
CC
T
V
EE
T
SFTCLK
HSYNC
VSYNC
V
EE
G
V
CC
G
CNTL0
BLU1 (5)
BLU1 (4)
V
CC
T
10 11
21
30
1
Decoder
CDR
PLL
Serial
to
Parallell
Converter
40
39
38
37
36
35
34
31
32
33
22
23
24
25
26
27
28
29
12 13 14 15 16 17 18 19 20
2
3
4
5
6
7
8
9
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
48
49
50
51
52
53
54
55
56
57
58
59
60
41
42
43
44
45
46
47
Cable
EQ
Fig. 1. Block Diagram & Pin out
2
CXB1452Q
Pin List
Power/Ground
Pin Name
V
CC
T
V
EE
T
V
CC
G
V
EE
G
V
CC
A
V
EE
A
V
EE
S
10, 20, 30, 40, 48, 70, 80
1, 11, 21, 31, 41, 49, 71
25, 32, 69, 76
26, 33, 68, 75
56
57
58
TTL power surpply , should be connected to 3.3V ± 5%
TTL ground, connected to 0V
Logical core power surpply, connected to 3.3V ± 5%
Logical core ground, connected to 0V
Analog power surpply, connected to 3.3V ± 5%
Analog ground, connected to 0V
Analog substrate, connected to 0V
Pin Number
Descriptions
Digital Signals
Pin Name
SFTCLK
RED1 (5 to 0)
GRN1 (5 to 0)
BLU1 (5 to 0)
RED0 (5 to 0)
GRN0 (5 to 0)
BLU0 (5 to 0)
HSYNC
VSYNC
CNTL (3 to 0)
PANEL (1, 0)
CKMODE
LOS
SDATAP/N
REFRQP/N
72
14, 15, 16, 17, 18, 19
6, 7, 8, 9, 12, 13
78, 79, 2, 3, 4, 5
42, 43, 44, 45, 46, 47
34, 35, 36, 37, 38, 39
22, 23, 24, 27, 28, 29
73
74
65, 66, 67, 77
62, 63
64
50
52, 53
51, 54
TTL out
TTL out
TTL out
TTL out
TTL out
TTL out
TTL in
TTL in
TTL out
Rx
Rx
Shift clock, for the data fetch at falling or rising edge
Pixel data input in 1 pixcel/sftclk mode
2nd pixel data input in 2 pixel/sftclk mode
High fixed in 1 pixcel/sftclk mode
1st pixel data input in 2 pixel/sftclk mode
Hsync data
Vsync data
Control data
Panel mode select switch
Clock mode select switch
Los of signal
Serial input
Refclk request
Pin Number
Type
Descriptions
Special
Pin Name
55, 61
59, 60
Polarity control of SFTCLK & TEST under fablication
External loop filter
Pin Number
Descriptions
TESTSB/DT
LPFA/B
3
CXB1452Q
Equivalent I/O circuit
300
6k
6k
V
CC
T
TTL-IN
V
EE
T
V
CC
G
V
EE
G
3k
V
CC
T
TTL-OUT
V
EE
T
(a) TTL input equivalent circuit
(b) TTL output equivalent circuit
SFTCLK, LOS
V
CC
T
TTL-OUT
V
EE
T
(b') TTL output equivalent circuit
REDxx, GRNxx, BLUxx, H/V sync, CNTLx
V
CC
A
LPFA
LPFB
V
EE
A
V
CC
G
SDATAP/N
REFRQP/N
V
EE
G
(c) LPFA/B equivalent circuit
(d) SDATAP/N REFRQP/N equivalent circuit
V
CC
A
TESTDT
V
EE
A
V
CC
G
V
EE
G
V
CC
T
TESTSB
V
EE
T
V
EE
G
V
CC
G
(e) TESTDT equivalent circuit
(f) TESTSB equivalent circuit
4
CXB1452Q
Electrical characteristics
Tab. 1. Absolute Maximum Rating
Description
Power supply voltage
TTL DC input voltage
TTL output current (High)
TTL output current (Low)
Serial output pin voltage
Ambient temperature
Storage temperature
V
CC
V
I
_T
I
OH
_T
I
OL
_T
Vsdout
Ta
Tstg
0.3
0.5
20
0
0.5
55
65
4
5.5
0
20
V
CC
+ 0.5
60
150
V
V
mA
'
mA
V
°C
°C
Under bias
Symbol
Min.
Typ.
Max.
Unit
Comments
Tab. 2. Recommended Operating Conditions
Description
Power supply voltage (Include V
CC
T5)
Ambient temperature
V
CC
Ta
3.135
0
3.3
3.465
60
V
°C
Symbol
Min.
Typ.
Max.
Unit
Comments
Tab. 3. DC Characteristics (Under the recommended conditons. See Tab. 2)
Description
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Output HIGH current (REFREQ)
Output LOW current (REFREQ)
Input dynamic range (SDATA)
Input dynamic range (SDATA)
Supply current
V
IH
_T
V
IL
_T
I
IH
_T
I
IL
_T
V
OH
_T
V
OL
_T
I
OH
_RQ
I
OL
_RQ
V
IM
_SD
V
ID
_SD
I
CC
2
0.5
400
2.25
0.1
7.4
V
CC
0.4
0.5
230
220
0
8.0
310
300
5.5
0.8
20
0.4
+0.1
8.6
V
CC
+ 0.2
+0.5
390
380
V
V
µA
µA
V
V
mA
mA
V
V
mA
mA
V
IN
= V
CC
V
IN
= 0
I
OH
= 0.2mA
I
OL
= 4mA
See Fig. 2
Common mode voltage
Differential voltage
2 pixel/sftclk, Outputs open
1 pixel/sftclk, Outputs open
Symbol
Min.
Typ.
Max.
Unit
Conditions
5
CXB1452Q
V
CC
A/G/T
V
EE
A/G/T
V
CC
CXB1452Q
A
55
61
A
51
54
Fig. 2. I
OH
_RQ and I
OL
_RQ DC measurement
Tab. 4. AC Characteristics (Under the recommended conditons. See Tab. 5)
Description
SFTCLK frequency
SFTCLK duty factor
Pixel/Sync/Cntl setup to
SFTCLK
Pixel/Sync/Cntl hold to
SFTCLK
SFTCLK rise time
SFTCLK fall time
Pixel/Sync/Cntl rise time
Pixel/Sync/Cntl fall time
CLOCK mode assert time
CLOCK mode deassert time
LOS signal assert time
LOS signal deassert time
Fsftclk
Dsftclk
Tsetup
Thold
Torc
Tofc
Tord
Tord
TAclk
TDclk
TAlos
TDlos
20.0
10.0
38.0
19.0
60.0
30.0
35
24.0
11.0
3.5
20.0
6.5
4.0
2.5
1.0
25.0
12.5
40.0
20.0
65.0
32.5
0.9
50
0.8
0.1
28.0
14.0
48.0
24.0
68.0
34.0
65
4.0
3.0
7.0
6.0
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
VGA, 1 pixel/sftclk mode
VGA, 2 pixel/sftclk mode
SVGA, 1 pixel/sftclk mode
SVGA, 2 pixel/sftclk mode
XGA, 1 pixel/sftclk mode
XGA, 2 pixel/sftclk mode
Vth = 1.4V, C
L
= 10pF
Vth = 1.4V, C
L
= 10pF
VGA, 1 pixel/sftclk 25MHz
SVGA, 1 pixel/sftclk 40MHz
XGA, 1 pixel/sftclk 65MHz
XGA, 2 pixel/sftclk 32.5MHz
Vth = 1.4V, C
L
= 10pF
VGA, 1 pixel/sftclk 25MHz
SVGA, 1 pixel/sftclk 40MHz
XGA, 1 pixel/sftclk 65MHz
XGA, 2 pixel/sftclk 32.5MHz
0.8V to 2.0V, C
L
= 10pF
2.0V to 0.8V, C
L
= 10pF
0.8V to 2.0V, C
L
= 10pF
2.0V to 0.8V, C
L
= 10pF
Symbol
Min.
Typ.
Max.
Unit
Conditions
6
CXB1452Q
Timing Chart
Tofc
Setup/hold time is refered from
rise edge in TESTSB/DT = GND or OPEN
fall edge in TESTSB/DT = V
CC
Torc
Vth
1/Fsftclk
2.0V
0.8V
SFTCLK
REDxx
GRNxx
BLUxx
H/Vsync
CNTLx
Thold
Tsetup
2.0V
0.8V
Tofd
Tord
Dsftclk/Fsftclk
Fig. 5. Refclk request timing
SDATAP
SDATAN
Pixel
Sync/Cntl
TAclk
error
TDclk
REFRQP
REFRQN
SftClk
Fig. 6. Idle mode timing
LOS
SDATAP
SDATAN
TDlos
TAlos
NRZ data
V
CC
A/G/T
V
EE
A/G/T
V
CC
CXB1452Q
Cprobe
oscillo-
scope
CL'
CL' + Cprobe = 10pF
TTLout
Fig. 3. SDATA waveform measurement
Fig. 4. TTL output timing
7
CXB1452Q
Operation mode
CXB1452Q supports 3 panel mode and 2 clock mode switched by the PANEL (1, 0) and CKMODE pin
according to the Tab. 5 & 6. The supporting color depth and clock rate are summarized in Tab. 7. These pins
are open High TTL inputs.
Tab. 5. Panel Mode select
PANEL1
L
L
H
H
L
H
L
H
VGA (640
×
480) 18bit color
SVGA (800
×
600) 18bit color
XGA (1024
×
768) 18bit color
not supported
PANEL0
Supporting panel size & color
Tab. 6. Clock Mode select
CKMODE
L
H
2 pixel/ShiftClock (2ppc)
1 pixel/ShiftClock (1ppc)
Supporting clock mode
Tab. 7. Operation Mode
Panel Mode
VGA
SVGA
XGA
1 pixel/SftClk
2 pixel/SftClk
1 pixel/SftClk
2 pixel/SftClk
1 pixel/SftClk
2 pixel/SftClk
18bit
18bit
18bit
18bit
18bit
18bit
25MHz
12.5MHz
40MHz
20MHz
65MHz
32.5MHz
25MHz
25MHz
40MHz
40MHz
65MHz
65MHz
600Mbps
600Mbps
960Mbps
960Mbps
1560Mbps
1560Mbps
Clock Mode
Color
Shift Clock
Dot Clock
Serial rate
TESTSB/TESTDT pins select the trigger edge of SFTCLK and test mode according to Tab. 8.
Tab. 8. SFTCLK polarity & TEST mode
TESTDT
GND
OPEN
V
CC
Fabricator reserved
TEST mode
TESTSB
GND
All TTL out
= Low
All TTL out
= High
OPEN
V
CC
LOS pin shows the absence of proper level of SDATA signal. LOS pin is High when connector is disconnected
or transmitter is idle.
Receiver operation
trigger = rising edge
Trigger = falling edge
8
CXB1452Q
Applications
CXB1452Q GVIF receiver is applied to the digital RGB signal transmittion for
P/C with LCD monitor
Video on demand system
Monitoring system
Graphical controller
Projector
Digital TV monitor
with GVIF transmitter, CXB1451Q.
RED0/GRN0/BLU0
are active in 2pixel/shiftclock
mode only
CXB1451Q GVIF Transmitter
STP or Twin axial
CXB1452Q GVIF Receiver
RED1 (5 to 0)
GRN1 (5 to 0)
BLU1 (5 to 0)
RED0 (5 to 0)
GRN0 (5 to 0)
BLU0 (5 to 0)
SYNC/CNTL
SHIFTCLOCK
6
6
6
6
6
6
6
PLL
Serial
to
Parallel
Converter
Cable
Equalizer
Decoder
6
6
6
6
6
6
6
Encoder
Parallel
to
Serial
Converter
Cable
Driver
PLL
RED1 (5 to 0)
GRN1 (5 to 0)
BLU1 (5 to 0)
RED0 (5 to 0)
GRN0 (5 to 0)
BLU0 (5 to 0)
SYNC/CNTL
SHIFTCLOCK
9
CXB1452Q
Application Cicuit (A)
Select SFTCLK polarity
according to Tab. 8
Select panel resolution
according to Tab. 5
(1) CHIP RESISTOR (1%)
(2) CHIP CAPACITOR
(3) FORMED BY THE PRINTED CIRCUIT PATTERN
(L = 0.5 to 1.0mm/W = 0.5 to 1.0mm)
(4) Idss rank 3mA
Rf (1)
100p (2)
0.1µ
(2)
0.1 to 0.4n (3)
0.1 to 0.4n (3)
0.1 to 0.4n (3)
V
CC
0.1 to 0.4n
(3)
E
1k
SW0
SW2
330
SW3
330
E
T
T
T
T
E
0.1µ
(2)
0.1µ
(2)
T
5
4
3
2
1
0
MSB
LSB
BLUE DATA
SFTCLK
HSYNC
VSYNC
DE
5
4
3
2
1
0
MSB
LSB
GREEN DATA
5
4
3
2
1
0
MSB
LSB
RED DATA
T
0.1µ
(2)
E
0.1µ
(2)
T
E
T
0.1µ
(2)
Differential cable
Connector
REFRQN
REFRQP
LOS
V
EE
T
LPFB
LPFA
V
EE
S
V
EE
A
V
CC
A
TESTSB
SDATAN
SDATAP
V
CC
T
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
V
EE
T
V
EE
T
BLU1 (3)
BLU1 (2)
BLU1 (1)
BLU1 (0)
GRN1 (5)
GRN1 (4)
GRN1 (3)
GRN1 (2)
V
CC
T
V
EE
T
GRN1 (1)
GRN1 (0)
RED1 (5)
RED1 (4)
RED1 (3)
RED1 (2)
RED1 (1)
RED1 (0)
V
CC
T
V
CC
T
BLU0 (0)
BLU0 (1)
BLU0 (2)
V
EE
G
V
CC
G
BLU0 (3)
BLU0 (4)
BLU0 (5)
V
EE
T
V
CC
T
GRN0 (0)
GRN0 (1)
GRN0 (2)
GRN0 (3)
GRN0 (4)
GRN0 (5)
V
EE
G
V
CC
G
V
EE
T
V
EE
G
TESTDT
PANEL1
PANEL0
CKMODE
CNTL3
CNTL2
CNTL1
V
CC
G
V
CC
T
V
EE
T
SFTCLK
HSYNC
VSYNC
V
EE
G
V
CC
G
CNTL0
BLU1 (5)
BLU1 (4)
V
CC
T
48
49
50
51
52
53
54
55
56
57
58
59
60
10 11
21
30
1
41
42
43
44
45
46
47
40
39
38
37
36
35
34
31
32
33
22
23
24
25
26
27
28
29
12 13 14 15 16 17 18 19 20
2
3
4
5
6
7
8
9
70
69
68
67
63
65
66
61
62
71
72
73
74
75
76
77
78
79
80
33µ
16V
47p
(1)
47p
(1)
100 (1)
150
(1)
150
(1)
Rf (1)
S
Rf = 470 (XGA/SVGA)
= 150 (VGA)
2SK303
(4)
T
64
Clock mode: 1 pixel/sftclk (1ppc)
Picture sync: H/V sync & DE
Color depth: 18bit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
10
CXB1452Q
Application Cicuit (B)
REFRQN
REFRQP
LOS
V
EE
T
100 (1)
150
(1)
150
(1)
S
Rf = 470 (XGA/SVGA)
= 150 (VGA)
2SK303
(4)
Select SFTCLK polarity
according to Tab. 8
Select panel resolution
according to Tab. 5
(1) CHIP RESISTOR (1%)
(2) CHIP CAPACITOR
(3) FORMED BY THE PRINTED CIRCUIT PATTERN
(L = 0.5 to 1.0mm/W = 0.5 to 1.0mm)
(4) Idss rank 3mA
Rf (1)
Rf (1)
100p (2)
0.1µ
(2)
0.1 to 0.4n (3)
0.1 to 0.4n (3)
0.1 to 0.4n (3)
V
CC
0.1 to 0.4n
(3)
E
1k
SW0
SW2
330
SW3
330
E
T
T
T
T
E
0.1µ
(2)
0.1µ
(2)
T
3
2
1
0
MSB
LSB
EVEN BLUE DATA
SFTCLK
ENABLE
3
2
1
0
MSB
LSB
EVEN GREEN DATA
3
2
1
0
MSB
LSB
EVEN RED DATA
T
0.1µ
(2)
E
0.1µ
(2)
T
E
T
0.1µ
(2)
Differential cable
Connector
33µ
16V
3
2
1
0
MSB
LSB
ODD BLUE DATA
3
2
1
0
MSB
LSB
ODD GREEN DATA
3
2
1
0
MSB
LSB
ODD RED DATA
ODD
PIXEL
Transmission order
of the PIXEL
EVEN
PIXEL
LPFB
LPFA
V
EE
S
V
EE
A
V
CC
A
TESTSB
SDATAN
SDATAP
V
CC
T
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
V
EE
T
V
EE
T
BLU1 (3)
BLU1 (2)
BLU1 (1)
BLU1 (0)
GRN1 (5)
GRN1 (4)
GRN1 (3)
GRN1 (2)
V
CC
T
V
EE
T
GRN1 (1)
GRN1 (0)
RED1 (5)
RED1 (4)
RED1 (3)
RED1 (2)
RED1 (1)
RED1 (0)
V
CC
T
V
CC
T
BLU0 (0)
BLU0 (1)
BLU0 (2)
V
EE
G
V
CC
G
BLU0 (3)
BLU0 (4)
BLU0 (5)
V
EE
T
V
CC
T
GRN0 (0)
GRN0 (1)
GRN0 (2)
GRN0 (3)
GRN0 (4)
GRN0 (5)
V
EE
G
V
CC
G
V
EE
T
V
EE
G
TESTDT
PANEL1
PANEL0
CKMODE
CNTL3
CNTL2
CNTL1
V
CC
G
V
CC
T
V
EE
T
SFTCLK
HSYNC
VSYNC
V
EE
G
V
CC
G
CNTL0
BLU1 (5)
BLU1 (4)
V
CC
T
48
49
50
51
52
53
54
55
56
57
58
59
60
10 11
21
30
1
41
42
43
44
45
46
47
40
39
38
37
36
35
34
31
32
33
22
23
24
25
26
27
28
29
12 13 14 15 16 17 18 19 20
2
3
4
5
6
7
8
9
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
47p
(1)
47p
(1)
Clock mode: 2 pixel/sftclk
Picture sync: ENABLE only
Color depth: 12bit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
11
CXB1452Q
Recommended Printed Circuit Board Structure
L1: Cu plate (18µm) + solder coat
L2: Cu plate (36µm)
I1: Adhesive Sheet (0.3mm ± 0.09mm)
I2: Fiber-glass epoxy core (0.8mm)
L3: Cu plate (36µm)
I3: Adhesive Sheet (0.3mm)
L4: Cu plate (18µm) + solder coat
Recommended Printed Circuit Board Pattern
SDATAP/SDATAN pins to the connector path
W = 0.50mm (Z0 = 50
)
other path
W = 0.25mm
POWER and special signal routing example
G
TESTDT
PANEL1
PANEL0
CKMODE
CNTL3
CNTL2
CNTL1
V
EE
G
V
CC
G
V
CC
T
V
EE
T
SFTCLK
HSYNC
VSYNC
V
EE
G
V
CC
G
CNTL0
BLU1 (5)
BLU1 (4)
V
CC
T
V
EE
T
BLU1 (3)
BLU1 (2)
BLU1 (1)
BLU1 (0)
GRN1 (5)
GRN1 (4)
GRN1 (3)
GRN1 (2)
V
CC
T
V
EE
T
GRN1 (1)
GRN1 (0)
RED1 (5)
RED1 (4)
RED1 (3)
RED1 (2)
RED1 (1)
RED1 (0)
V
CC
T
V
CC
T
GRN0 (0)
GRN0 (1)
GRN0 (2)
GRN0 (3)
GRN0 (4)
GRN0 (5)
V
EE
G
V
CC
G
V
EE
T
V
CC
T
BLU0 (0)
BLU0 (1)
BLU0 (2)
V
EE
G
V
CC
G
BLU0 (3)
BLU0 (4)
BLU0 (5)
V
EE
T
LPFB
LPFA
V
EE
S
V
EE
A
V
CC
A
TESTSB
REFRQN
SDATAN
SDATAP
REFRQP
LOS
V
EE
T
V
CC
T
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0 (4)
RED0 (5)
V
EE
T
40
21
80
61
60
41
20
1
G
G
G
E
E
G
G
E
G
E
G
G
T
T
T
T
T
T
T
T
L2 doesn't have plane
in this area
0.5mm
To LOS
Through hole to the GND plane (L2)
Through hole to the V
CC
E/V
CC
G plane (L3)
Through hole to the V
CC
T plane (L3)
Chip capacitor
Chip resistor
E
T
G
FET
12
CXB1452Q
CENTER 32.50MHz
SPAN 10.00MHz
REF LVL
0dBm
VBW 100kHz
SWP 50.0ms
D
ATTEN 10dB
RL 0dBm
10dB/
SFTCLK
32.5MHz
RBW 100kHz
SFTCLK
65MHz
TTL output
B15
65Mb/s
TTL output
1V
1V
5ns
TTL output waveform with C
L
= 10pF
SFTCLK Power spectrum
13
CXB1452Q
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
QFP-80P-L03
QFP080-P-1414
0.6g
80PIN QFP (PLASTIC)
16.0 ± 0.4
14.0 0.1
+ 0.4
0.3 0.1
+ 0.15
0° to 10°
0.5 ±
0.2
0.1 0.1
+ 0.15
(15.0)
0.127 0.05
+ 0.1
1.5 0.15
+ 0.35
40
21
20
1
41
60
61
80
M
0.24
0.1
0.65
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