Digital CCD Camera Head Amplifier

Description

The CXA2056Q is a bipolar IC developed as a

head amplifier for digital CCD cameras. This IC

provides the following functions: correlated double

sampling, AGC for the CCD signal, GCA for the low-

band chroma signal, AMP for high-band chroma and

line signals, A/D sample and hold, blanking, A/D

reference voltage, and an output driver.

Features

· High sensitivity made possible by a high-gain AGC

amplifier

· Blanking function provided for the purpose of

calibrating the CCD output signal black level

· Regulator output pin provided for A/D converter

reference voltage

· Built-in GCA and AMP for amplifying video signals

(chroma and line signals) from external sources

· Built-in sample-and-hold circuits for camera signals

required by external A/D converters

Absolute Maximum Ratings

· Supply voltage

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

1160

Operating Conditions

Supply voltage

1, 2, 3

3 to 3.3

Applications

Digital CCD cameras

Structure

Bipolar silicon monolithic IC

E96119A8X-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2056Q

32 pin QFP (Plastic)

CXA2056Q

Block Diagram and Pin Configuration

SHIFT

BUF

SH1

SH2

SH3

VIDC

SHIFT

REF

DMSW1

DMSW2

CH
SW

CAM

OBSW

CENT

MODE CONTROL

POWER SAVE CONTROL

LOSW

OFFSET

CVSW

CENT

BLK SW

PBRFC

DIN

ICONT

LIN/CH

GND2

RFCONT

AGCCLP

CLPOB

XRS

PBLK

OFFSET

VRT

VRB

.
C

VISW

LISW

CDS

CLP1

CDS

CLP2

LIN

CLP

LIN

CH AMP

GCA

CAM

DRV

VIDEO

DRV

LOUT

CLP

DRV

AGC

CXA2056Q

Pin Description

1, 2, 3 = 3V)

No.

Symbol

Pin voltage

Equivalent circuit

Description

MODE1

Camera and video
signal selector.
Composite video
signal and high-band
chroma/low-band
chroma signal
selector of the video
signal.
For details on the
selection conditions
for each mode, refer
to the diagram of the
Electrical
Characteristics
Measurement Circuit.

MODE2

MODE3

Power saving mode.

N.C

No connection;
normally ground.

23
30

GND3
GND1
GND2

Ground.

LOUTCLP

Capacitor connection
for LOUTCLP which
clamps the output
minimum level in
modes which pass
the composite video
signal.
(Recommended
value: 0.1µF)

VTH = 1.5V

GND

Approx. 1.1V

145

75k

50k

10µA

1.5V

2µA

100µA

38k

90k

22k

12k

145

1.1V

CXA2056Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

DRVOUT

Driver output for A/D
converter capable of
DC coupling.

Dynamic range
= 1Vp-p

· Camera

mode (CAM)
V

to V

100mV

· Composite

video mode
(LIN)
V

+ 50mV

= approx.

1.4V

· Chroma

mode
(CH, CL)
Center
voltage =
(V

)/2

= approx.

1.85V

VRB

1.35V regulator
output.

Be sure to decouple
this pin near the IC
pins to prevent the
oscillation and external
noise when this pin is
not used.
(Recommended
capacitor value: 4.7µF)

20
27

Power supply.

1.35V

2.35V

VRT

2.35V regulator
output.

Be sure to decouple
this pin near the IC
pins to prevent the
oscillation and external
noise when this pin is
not used.
(Recommended
capacitor value: 4.7µF)

100µA

5090

4072

509

30k

10p

1.4

1.85V

30k

SW3

SW1

SW2

2.4mA

CAM signal

VIDEO signal

50µA

SW1

145

CONT

3.2 to 6.4mA

200µA

50µA

25µA

OFFSET

0 to
50µA

SW1

= 2.35V

= 1.35V

SW1 SW2

Mode

SW3

CAM

LIN

CH, CL

0: Open
1: Closed

200

30k

16.5k

13.5k

145

1.35V

110µA

30k

6.5k

23.5k

145

2.35V

220µ

55µ

200

CXA2056Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

OFFSET

Controls the output
offset during camera
mode.

When 3V: V

When 1.5V:

+ 100mV

When 0V
(preset mode):

+ 35mV

1.5 to 3V

30k

50k

1.5k

25k

145

50µA

1.85V

PBLK

Camera signal
preblanking pulse
input.

Active when Low only
during camera mode.
Calibrates the black
level of the AGC output
waveform.
When PBLK is Low,
the DRVOUT potential
is forced to V

VTH = 1.85V

145

50µA

30k

1.85V

30k

XRS

Camera signal
sample-and-hold
pulse input.

VTH = 0.68V

24k

0.68V

770µA

40µA

97µ

145

CLPOB

Clamp pulse used to
clamp the optical
black portion of the
camera signal after it
passes through the
AGC amplifier.

VTH = 1.5V

145

50µA

30k

1.5V

30k

Active: Low

Sampling

Active: Low

CXA2056Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

AGCCLP

AGC clamp capacitor.
(Recommended
value: 0.1µF)

Approx. 1.3V

AGCCONT

AGC gain control.

When 1.5V: 1dB

(Minimum gain)

When 3.0V: +31.5dB

(Maximum gain)

1.5 to 3.0V

50k

145

200µA

3.4k

200µA

2.14V

100µA

300µA

100µA

2.29V

CONT

3.4k

3.3k

CCDLEVEL

Enables monitoring of
the SH3 output
camera signal.

DIN input
CCD signal
black level:
approx. 2.2V

SHP

Preset level sample-
and-hold pulse input.

SHD

Data level sample-
and-hold pulse input.

VTH = 0.65V

500

340

100µA

36k

10k

0.65V

365µA

20µA

145

Sampling

CXA2056Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

CLPDM

Clamp pulse used to
clamp the dummy
pixel portion of the
input CCD signal.

VTH = 1.5V

145

50µA

30k

1.5V

25
26

PIN
DIN

ICONT

CCD signal input.

DRVOUT output
waveform rise time
control.

When 1.5V:

Maximum rise time

When 3V:

Minimum rise time

Black level:
approx. 2.1V

1.5 to 3V

145

200µA

50µA

23k

14k

15µA

145

100µA

15k

45k

2.25V

LIN/CH

Common input for the
composite video
signal (LIN) and high-
band chroma signal
(CH).

Clamp
potential
during
LIN mode:
approx. 1.46V

During
CH mode:
approx. 1.85V

145

50µA

25µA

200µA

11.5k

18.5k

1.85V

CH mode

100µA

LIN mode

2µA

10k

30k

+ 50mV

54k

Active: Low

CXA2056Q

Electrical Characteristics

(Ta=25°C, V

1, 2, 3 = 3V)

Camera
mode

LINE mode

CH mode

CL mode

PS mode

Maximum
gain

Minimum
gain

Range of gain
variance

Dynamic
range
maximum

Dynamic
range
typical

Offset high

Offset low

Offset
preset

level

Offset

LIN mode
gain

CH mode
gain

CL mode
maximum gain

CL mode
minimum gain

Dynamic
range

DCH

PCL

A CONT
max.

A CONT
min.

AGC G

AGCmax.
D

AGC

TYP

CAOF
high

CAOF
low

CAOF
pre

VRTO

VRBO

BLKOF

LIN G

CH G

RF
CONmax.

RF
CONmin.

SH3 D

AGCCONT = 1.5V, open between V

and V

MODE1 = 3V, MODE2 = 0V
MODE3 = 0V, PS = 3V, I

CONT

= 3V

Open between V

and V

MODE1 = 0V, MODE2 = 0V,
MODE3 = 0V, PS = 3V

Open between V

and V

MODE1 = 0V, MODE2 = 3V,
MODE3 = 3V, PS = 3V

RFCONT = 0.3V, open between V

and V

MODE1 = 0V, MODE2 = 3V,
MODE3 = 0V, PS = 3V

PS = 0V

DIN = 1µs, 20mVp-p pulse
AGCCONT = 3V, I

CONT

= 3V

DIN = 1µs, 500mVp-p pulse
AGCCONT = 1.5V, I

CONT

= 3V

A CON max. A CON min.

AGCCONT = 3V
DRVOUT output signal at saturation level

AGCCONT = 2V
DRVOUT output signal at saturation level

Camera mode
OFFSET = 1.5V

Camera mode
OFFSET = 3.0V

Camera mode
OFFSET = 0V

With a 400

load

With a 400

load

With a 400

load

BLKOF (PBLK = 3V) BLKOF (PBLK = 0V)

LIN/CH = 15kHz, 500mVp-p,
Sine wave + offset voltage

LIN/CH = 3MHz, 500mVp-p, sine wave

RFCONT = 2.7V
15kHz 80mVp-p sine wave

RFCONT = 0.3V
15kHz 500mVp-p sine wave

DIN = 1µs, 1Vp-p pulse

Item

Symbol

Conditions

Min.

Typ.

Max. Unit

Current
consump-
tion

AGC

DRV

REF

BLK

AMP

GCA

28.5

27.1

800

900

2300

1300

950

--10

2.5

9.5

600

41.0

13.9

12.2

3.4

31.3

0.8

32.1

895

955

2342

1359

983

3.43

3.18

12.7

4.0

815

1.4

2400

1400

1050

4.5

2.5

SH3

CXA2056Q

Electrical Characteristics Measurement Circuit

GND

V1
3V

GND

V2
3V

V3
3V

GND

V4
3V

GND

SW2

SW1

SW4

SW3

GND

V5
1.85V

C5
0.1µ

R1
10k

GND

C6
70pF

PL5

XRS

PL4

CLPOB

C7
0.1µF

VRT

VRB

C9
4.7µF

400

SW6

OFF

C8
4.7µF

OFFSET

V6
0 to 3V

C4
1µF

C3
1µF

DIN

AC
V8

C2
0.047µF

PBRFC

AC
V13

V12
0.3 to 2.7V

RFCONT

C1
0.1µF

LIN/

AC
V11

SW5

V10
0 to 3V

OFF

GND

PL1

GND

PL2

GND

PL3

GND

.
C

V7
1.5 to 3V

AGCCLP

ICONT

GND2

.
C

V9
1.5 to 3V

PL6

PBLK

SW1

SW2

SW3

SW5 SW4

MODE

OFF

CAM

LIN

POWER SAVE

CXA2056Q

Application Circuit

GND

0.1µF

.
C

PBLK

XRS

CLPOB

0.1µF

VRT

VRB

4.7µF

OFFSET

0 to 3V

1µF

DIN

0.047µF

PBRFC

0.3 to 2.7V

RFCONT

0.1µF

LIN/CH

GND

.
C

AGCCONT

1.5 to 3V

AGCCLP

ICONT

GND2

1µF

CCD

LIN/CH

PBRFC

A/D IN

A/D

CLPDM

SHD

SHP

RFCONT

ICONT

1.5 to 3V

OFFSET

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXA2056Q

Description of Operation
Refer to the Block Diagram.

1. Camera signal processing system
Process the video signal processing pins as follows only in camera mode.

<7> LOUTCLP ... Connect to GND.
<29> LIN/CH

... Connect to GND.

<31> RFCONT ... Connect to GND via the capacitor (approx. 0.01µF).
<32> PBRFC

... Connect to GND.

Operating conditions
The camera signal processing system operates when PS is High, MODE1 is Low, MODE2 is Low and MODE3
is High, or when PS is High, MODE1 is High, MODE2 is Low and MODE3 is Low.

Camera signal processing system timing chart (when V

= 3V)

PBLK

(10µ during the idle

transfer interval)

Sig interval

OPB interval

Idle transfer
interval

Sig interval

Precharge level

Signal level

2.1V

[

2µs

0.65V

Black level

Basic black
level

2µs

0.65V

10µs

1.35V

Approx. V

+ 35mV when OFFSET = 0V

Approx. V

+ 100mV when OFFSET = 1.5V

Approx. V

when OFFSET = 3V

CCD output

SHP

SHD

SH1 output

SH2 output

SH3 output

CLPDM
(2µ dummy bit portion during
the idle transfer interval)

XRS

CLPOB

(2µ during the OPB

interval)

CAMSH

output

BLK SW output

CAM DRVOUT output

AGC output

( N)

SH3 output
SH2 output

[

CXA2056Q

CDS (SH1, SH2, SH3):

The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)

is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output

by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the

sample-and-hold circuits for the pre-charge level; SH3 is the sample-and-hold circuit for the signal level.

CDSCLP 1, 2:

CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer

interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([

1], [

2]) of SH2 and SH3

in line with V

REF

. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for

the signal level.

AGC:

AGC is the gain control amplifier for the camera signal.

The gain can be varied from 1 to +31dB by adjusting the AGCCONT voltage control V

AGCCONT

from 1.5 to

3.0V.

CAM SH:

CAM SH is the sample-and-hold circuit for the camera signal processing system; it synchronizes the data read-

in timing for the external A/D.

Sampling is possible according to the approximately 10ns sampling pulse width input to XRS.

AGCCLP:

The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB

interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current

so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the

OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin.

DC SHIFT:

This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the

AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black

level is maintained at its previous setting.

BLK SW:

The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not

fall below the basic black level and replacing the DC potential with V

. ([

4])

The signal is blanked when PBLK is low.

CVSW:

When the MODE1, 2, 3 and PS pin voltages are set so that the camera signal processing system operates,

CVSW conducts the CAMDRV output (camera signal) into the DRVOUT. In addition, when these voltages are

set so that the video signal processing system operates, CVSW conducts the VIDEODRV output (video signal)

into the DRVOUT.

CXA2056Q

OFFSET:

OFFSET controls the CAMDRV output waveform black level offset.

In the camera signal processing system camera mode, the OFFSET pin is enabled, permitting adjustment of

the offset for the [OFFSET] and DRVOUT camera signals. ([

5]) The voltage controlled by OFFSET is output

as the CAMDRV output DC offset via AGCLP, DCSHIFT, CAMSH, and BLKSW.

When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from V

+ 100mV to V

In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to V

+ 35mV.

CAMDRV:

CAMDRV operates in the camera signal processing system mode, driving the external A/D. The current that

flows to the last-stage amplifier in CAMDRV is controlled by applying voltage to the ICONT pin, making it

possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The

variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise

time for the external A/D input capacitance can be selected.

DRV, V

DRV:

These are the external A/D reference voltage drivers. These circuits are connected to A/D V

and V

supplying 2.35V and 1.35V, respectively, when V

is 3V. The IC's internal primary voltage is also generated

on the basis of the V

and V

voltages. (V

, V

, and V

CENT

)

MODE CONTROL & POWER SAVE CONTROL:

This block selects the mode governing the operation of the camera signal system and the video signal system

through the selection of High and Low potential for the MODE1, 2, 3, and PS pins. The PS pin is the POWER

SAVE pin; the power saving function operates when this pin is Low.

2. Video signal processing system

Operating conditions

The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode.

The video signal processing system operates in LIN signal mode when PS is High, MODE1 is High, MODE2 is

Low and MODE3 is High, or when PS is High, MODE1 is Low, MODE 2 is Low and MODE3 is Low.

The video signal processing system operates in CH signal mode when PS is High, MODE1 is Low, MODE2 is

High and MODE3 is High.

The video signal processing system operates in CL signal mode when PS is High, MODE1 is Low, MODE2 is

High and MODE3 is Low, or when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High.

Video signal processing system timing chart (when V

= 3V)

LIN mode

1.46V

1.4V

LIN/CH input

· LIN CHAMP output (3.5dB)

· DRVOUT output

CXA2056Q

LIN signal mode

In LIN signal mode, LINSW and LOSW close, VISW is set to "1" and the video signal passes through CVSW.

In addition, LINCHAMP, LINCLP, LOUTCLP, VIDC SHIFT, and VIDEO DRV all operate.

LINCLP:

LINCLP is an input clamp circuit that clamps the video composite signal sync level.

The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip

clamps the input signal at V

(= 1.4V) to allow full input. The input level and frequency are respectively

571mVp-p (Max.) and DC is up to 7MHz.

LINCHAMP:

LINCHAMP amplifies the LIN signal and the CH (high-band chroma) signal; the gain is fixed at 3.5dB.

VISW:

VISW switches the LIN signal, the CH (high-band chroma) signal, and the CL (low-band chroma) signal. The

signals are switched according to the mode selection.

LOUTCLP:

LOUTCLP is an output clamp circuit that clamps the sync level of the video composite signal that is output

from VIDEO DRV.

Because the VIDEO DRV output signal is fully input to the external A/D, the clamp level is set to V

(= 1.4V).

If the sync level of the signal output from VIDEO DRV drops below V

, LOUTCLP operates: the LOUTCLP

current flows so that the sync level equals V

, and the LOUTCLP potential is set. A clamping capacitor is

connected to the LOUTCLP pin.

VIDC SHIFT:

VIDC SHIFT functions when LOUTCLP operates, following the LOUTCLP potential and forcing a DC shift of

the VIDEO output signal sync level to V

VIDEO DRV:

VIDEO DRV outputs the video signal (LIN, CH, CL) to the external A/D in video signal processing mode.

CXA2056Q

CH (high-band chroma) signal mode

In CH mode, CHSW closes, VISW is set to "2" and the video signal passes through CVSW. In addition,

LINCHAMP and VIDEO DRV operate.

The video high-band chroma signal is input to the LIN/CH pin. V

expands the input dynamic range and sets a

center DC bias so that the center potential of the SIN signal is 1.85V to allow full input. The input level and

frequency of the CH signal are respectively 470mVp-p (Max.) and from 1 to 7MHz.

CENT

is a DC bias circuit that operates when the CH signal is output to VIDEO DRV. The DC bias potential is

generated from V

and V

, and is set to 1.85V.

CH mode

1.85V

LIN/CH input

· LINCH AMP output
(3.5dB)
· DRVOUT output

1.85V

CXA2056Q

CL (low-band chroma) signal mode

In CL mode, VISW is set to "3" and the video signal passes through CVSW. In addition, CLGCA and VIDEO

DRV operate.

The video low-band chroma signal is input to the PBRFC pin. V

expands the input dynamic range and sets a

center DC bias so that the center potential of the SIN signal is 1.9V to allow full input. The input level and

frequency of the CH signal are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz.

CLGCA:

The CLGCA amplifier controls the gain of the CL signal input to the PBRFC pin. The gain can be varied from

4 to +12.5dB by adjusting the RFCONT voltage from 0.3 to 2.7V. The phase of the CLGCA output waveform

is reversed in DRVOUT.

CENT

is a DC bias circuit that operates when the CL signal is output to VIDEO DRV. The DC bias potential is

generated from V

and V

, and is set to 1.85V.

CL mode

1.9V

PBRFC input

· CLGCA output
(4 to +12.5dB)
· DRVOUT output

1.85V

CXA2056Q

Example of Representative Characteristics

CAM mode AGCCONT control supply voltage characteristics

AGCCONT

vs. Gain

AGCCONT

[V]

1.5

2.0

2.5

3.0

3.3

i
n

[
d

]

Tc = 27°C

= 3V

= 3.15V

= 3.3V

CAM mode OFFSET control supply voltage characteristics

OFFSET

vs. OFFSET

OFFSET

[V]

1.0

2.0

3.0 3.3

100

[
m

]

Tc = 27°C

= 3.3V

= 3V

115

CL mode RFGCA gain control supply voltage characteristics

RFCONT

vs. Gain

RFCONT

[V]

1.0

2.0

3.0 3.3

i
n

[
d

]

Tc = 27°C

= 3V

= 3.15V

= 3.3V

=) 0

CXA2056Q

CAM mode AGCCONT control temperature characteristics

AGCCONT vs. Gain

AGCCONT [V]

1.5

2.0

2.5

3.0

i
n

[
d

]

= 3.0V

CAM mode OFFSET control temperature characteristics

OFFSET

vs. OFFSET

OFFSET

[V]

1.0

2.0

3.0

100

[
m

]

= 3.0V

150

Tc = 20°C
Tc = +27°C
Tc = +75°C

CL mode RFGCA gain control temperature characteristics

RFCONT

vs. Gain

RFCONT

[V]

1.0

2.0

3.0

2.7

i
n

[
d

]

0.3

= 3V

Tc = 20°C
Tc = +27°C
Tc = +75°C

=) 0

Tc = 20°C
Tc = +27°C
Tc = +75°C

CXA2056Q

CAM mode maximum signal amplitude

temperature characteristics (Min. gain)

Tc vs. Vout

Tc [°C]

0.6

t

[
V

-
p

]

0.7

0.8

100

0.53

= 3.0V, AGCCONT = 1.5V

Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =

870mVp-p
800mVp-p
750mVp-p
700mVp-p
600mVp-p

0.9

DIN = 870mVp-p

DIN = 800mVp-p

DIN = 750mVp-p

DIN = 700mVp-p

DIN = 600mVp-p

LIN, CH mode LINCHAMP gain

temperature characteristics

Tc vs. Gain

Tc [°C]

i
n

[
d

]

3.5

= 3.0V

LIN mode
CH mode

[V]

i
n

[
d

]

3.15

3.3

3.5

LIN, CH mode LINCHAMP gain supply

voltage characteristics

vs. Gain

Tc = 27°C

CH mode
LIN mode

CAM mode maximum signal amplitude

temperature characteristics (Max. gain)

Tc vs. Vout

Tc [°C]

0.8

t

[
V

-
p

]

0.9

1.0

100

0.75

= 3.0V, AGCCONT = 3.0V

Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =

28mVp-p
24mVp-p
21mVp-p

30.99dB 30.99dB

30.76dB

31.41dB 31.41dB

31.03dB

31.45dB 31.45dB

31.12dB

DIN = 28mVp-p

30.99 dB

+0
0.23

DIN = 24mVp-p

31.41 dB

+0
0.38

DIN = 21mVp-p

31.45 dB

+0
0.33

Gain temperature
characteristics from
20 to +100°C

CXA2056Q

CH, LIN, CL mode DRVOUT output DC voltage
temperature characteristics

= 3.0V

Tc [°C]

1.4

1.9

1.85

1.8

1.75

1.7

1.65

1.6

1.55

1.5

1.45

CL mode

CH mode

LIN mode

Tc [°C]

I
N

1.4

1.9

1.85

1.8

1.75

1.7

1.65

1.6

1.55

1.5

1.45

CL mode

CH mode

LIN mode

= 3.0V

Tc vs. DCIN

, V

 V

temperature characteristics

Tc vs. V

, V

 V

= 3.0V

Tc [°C]

,

V

[
V

]

0.8

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

CH, LIN, CL mode input pin DC voltage
temperature characteristics

Tc vs. DCOUT

CXA2056Q

CL mode 2nd/3rd harmonic distortion
temperature characteristics (Max. gain)

= 3.0V, RFCONT = 2.7V

f = 700kHz

Tc [°C]

/
3

r
d

r
m

i
c

i
s

t
o

r
t
i
o

[
d

]

2nd: out = 0.75Vp-p

3rd: out = 0.75Vp-p

3rd: out = 0.3Vp-p

2nd: out = 0.3Vp-p

LIN mode 2nd/3rd harmonic distortion
temperature characteristics

= 3.0V

f = 5MHz

Tc [°C]

/
3

r
d

r
m

i
c

i
s

t
o

r
t
i
o

[
d

]

2nd: out = 0.9Vp-p

3rd: out = 0.9Vp-p

3rd: out = 0.75Vp-p

2nd: out = 0.75Vp-p

CH mode 2nd/3rd harmonic distortion
temperature characteristics

= 3.0V

f = 5MHz

Tc [°C]

/
3

r
d

r
m

i
c

i
s

t
o

r
t
i
o

[
d

]

2nd: out = 0.75Vp-p

3rd: out = 0.75Vp-p

3rd: out = 0.9Vp-p

2nd: out = 0.9Vp-p

CL mode 2nd/3rd harmonic distortion
temperature characteristics (Min. gain)

Tc [°C]

/
3

r
d

r
m

i
c

i
s

t
o

r
t
i
o

[
d

]

2nd: out = 0.75Vp-p

3rd: out = 0.75Vp-p

2nd: out = 0.3Vp-p

3rd: out = 0.3Vp-p

= 3.0V, RFCONT = 0.3V

f = 700kHz

Tc vs. 2nd/3rd harmonic distortion

Part Number CXA2056Q