Document Outline

• Preface
• 1 Overview
  • 1.1 Features
  • 1.2 Ordering Codes
  • 1.3 Logic Symbol for µP Mode
  • 1.4 Logic Symbol for Stand-Alone Mode
  • 1.5 System Integration
    • 1.5.1 PCM 2 Systems
    • 1.5.2 PCM 4 with FAX/Modem Features
    • 1.5.3 Repeater
    • 1.5.4 Wireless Local Loop
    • 1.5.5 TE Applications
    • 1.5.6 Dual Mode U and S Terminals and PC Cards
    • 1.5.7 NT-PBX
    • 1.5.8 LT Application and Access Network
    • 1.5.9 NT1
• 2 Pin Descriptions
  • 2.1 Pin Configuration
    • 2.1.1 P-LCC-44 Package
    • 2.1.2 T-QFP-64 and M-QFP-64 Packages
  • 2.2 Pin Definitions and Functions
    • 2.2.1 Pin Definition in Stand-Alone Mode
      • 2.2.1.1 Mode Selection Pins
      • 2.2.1.2 Power Supply Pins
      • 2.2.1.3 IOM®-2 Pins
      • 2.2.1.4 IOM®-2 Control Pins
      • 2.2.1.5 U-Interface Pins
      • 2.2.1.6 Power Controller Pins
      • 2.2.1.7 Clocks
      • 2.2.1.8 Miscellaneous Function Pins
      • 2.2.1.9 Test Pins
    • 2.2.2 Pin Definition in Microprocessor Mode
      • 2.2.2.1 Mode Selection Pins
      • 2.2.2.2 Data, Address and µP Selection Pins
      • 2.2.2.3 µP Control Pins
      • 2.2.2.4 Power Supply Pins
      • 2.2.2.5 IOM®-2 Pins
      • 2.2.2.6 U-Interface Pins
      • 2.2.2.7 Power Controller Pins
      • 2.2.2.8 Clocks
      • 2.2.2.9 Miscellaneous Function Pins
      • 2.2.2.10 Test Pin
  • 2.3 Microprocessor Bus Interface (Overview)
• 3 Functional Description
  • 3.1 Functional Overview
  • 3.2 Setting Operating Modes
    • 3.2.1 Basic Operating Mode
    • 3.2.2 Test Modes
    • 3.2.3 DOUT Driver Modes
    • 3.2.4 IOM®-2 Enable/Disable Mode
    • 3.2.5 EOC Auto/Transparent Mode
    • 3.2.6 Monitor Procedure Time-Out (MTO)
    • 3.2.7 Setting IOM®-2 Bit Clock Mode
  • 3.3 Block Diagram
  • 3.4 Transceiver Core
    • 3.4.1 System Interface Unit
    • 3.4.2 Receiver
    • 3.4.3 Line Interface Unit
  • 3.5 U-Interface
    • 3.5.1 Output and Input Signals
    • 3.5.2 U -Frame Structure
  • 3.6 IOM®-2 Interface
    • 3.6.1 IOM®-2 Frame Structure
      • 3.6.1.1 Multiplexed Timing Mode
      • 3.6.1.2 Plain Timing Mode
      • 3.6.1.3 Terminal Timing Mode
    • 3.6.2 IOM®-2 Command / Indication Channels
      • 3.6.2.1 Active C/I Channel
      • 3.6.2.2 C/I Channel 1
    • 3.6.3 IOM®-2 Monitor Channel
      • 3.6.3.1 Active Monitor Channel
      • 3.6.3.2 Monitor Channel 1
      • 3.6.3.3 Monitor Procedure Time-Out
    • 3.6.4 Activation/Deactivation of IOM®-2 Clocks
  • 3.7 Clocks
    • 3.7.1 LT Mode
    • 3.7.2 NT and TE Mode
    • 3.7.3 NT-PBX
    • 3.7.4 Repeater Modes
      • 3.7.4.1 NT Repeater
      • 3.7.4.2 LT Repeater
    • 3.7.5 COT-512 and COT-1536 Mode
    • 3.7.6 Microprocessor Clock Output
  • 3.8 Microprocessor Interface
  • 3.9 S/G Bit and BAC bit Control
  • 3.10 Power Controller Interface
  • 3.11 Power Status
  • 3.12 Undervoltage Detection
  • 3.13 Watchdog Timer
  • 3.14 Power On Reset (POR)
  • 3.15 Reset Behavior
  • 3.16 Test Block
• 4 Operational Description
  • 4.1 Microprocessor Access to IOM®-2 Channels
    • 4.1.1 B-Channel Access
    • 4.1.2 D-Channel Access
    • 4.1.3 C/I Channel Access
    • 4.1.4 Monitor Channel Access
      • 4.1.4.1 Monitor Channel Protocol
  • 4.2 Access to U-Interface
    • 4.2.1 Access to Data Channels of U-Interface
    • 4.2.2 Access to EOC of U-Interface
    • 4.2.3 Access to the Single Bits of U-Interface
      • 4.2.3.1 Single Bits Transmission on U
      • 4.2.3.2 Single Bits Reception from U
    • 4.2.4 Setting Superframe Marker
  • 4.3 Layer 1 Activation and Deactivation
    • 4.3.1 Complete Activation Initiated by LT
    • 4.3.2 Activation with ACT-Bit Status Ignored by the Exchange Side
    • 4.3.3 Complete Activation Initiated by TE
    • 4.3.4 Complete Deactivation
    • 4.3.5 Partial Activation (U Only)
    • 4.3.6 Activation Initiated by LT with U Active
    • 4.3.7 Activation Initiated by TE with U Active
    • 4.3.8 Deactivating S/T-Interface Only
    • 4.3.9 Activation Initiated by LT with Repeater
    • 4.3.10 Activation Initiated by TE with Repeater
    • 4.3.11 Loss of Synchronization / Signal at Repeater
    • 4.3.12 Deactivation with Repeater
    • 4.3.13 Activation Attempt Initiated by NT in NT-Auto Activation Mode
    • 4.3.14 Activation in the µP-NT Mode
    • 4.3.15 Upstream Wake-Up Indication in the LT Repeater Mode
  • 4.4 State Machines
    • 4.4.1 State Machine Notation Rules
    • 4.4.2 State Machine in LT Modes
      • 4.4.2.1 LT Modes State Diagram
      • 4.4.2.2 Transition Criteria in LT Modes
      • 4.4.2.3 Output Signals and Indications in LT Modes
      • 4.4.2.4 LT States
    • 4.4.3 State Machine in NT Modes
      • 4.4.3.1 NT Modes State Diagram
      • 4.4.3.2 Transition Criteria in NT Modes
      • 4.4.3.3 Output Signals and Indications in NT Modes
      • 4.4.3.4 NT States
    • 4.4.4 State Machine in Repeater Modes
  • 4.5 Monitoring Transmission Quality
    • 4.5.1 Block Error Counters
      • 4.5.1.1 NEBE Counter
      • 4.5.1.2 FEBE Counter
      • 4.5.1.3 Testing Block Error Counters
  • 4.6 Chip Internal Test Options
    • 4.6.1 Self-Test
    • 4.6.2 Receiver Coefficient Values
  • 4.7 Test Loop-Backs
    • 4.7.1 Analog Loop-Back (No. 1/No. 3)
    • 4.7.2 Partial and Complete Loop-Back (No. 2)
      • 4.7.2.1 Complete Loop-Back
      • 4.7.2.2 Single-Channel Loop-Backs
      • 4.7.2.3 Repeater Loop-Back (No. 1A)
      • 4.7.2.4 Codes
  • 4.8 Chip Identification
  • 4.9 Access to Power Status Pins
    • 4.9.1 Monitoring Primary and Secondary NT Power Supply
    • 4.9.2 Monitoring Remote Power Feed Circuit in LT Modes
    • 4.9.3 Monitoring Power Feed Current in LT Modes
    • 4.9.4 Access to Pin DISS
  • 4.10 Access to Power Controller Interface
    • 4.10.1 Data Port
    • 4.10.2 Interrupt
  • 4.11 S/G Bit and BAC Bit Operations
    • 4.11.1 State Machine
    • 4.11.2 Indication of S/G Bit Status on Pin SG
• 5 Register Description
  • 5.1 Interrupt Structure
    • 5.1.1 Monitor-Channel Interrupt Logic
  • 5.2 Detailed Register Description
    • 5.2.1 ISTA-Register
    • 5.2.2 MASK-Register
    • 5.2.3 STCR-Register
    • 5.2.4 ADF2-Register
    • 5.2.5 MOSR-Register
    • 5.2.6 MOCR-Register
    • 5.2.7 CIRU-Register
    • 5.2.8 CIWU-Register
    • 5.2.9 CIRI-Register
    • 5.2.10 CIWI-Register
    • 5.2.11 ADF-Register
    • 5.2.12 SWST-Register
    • 5.2.13 B-Channel Access Registers
    • 5.2.14 D-Channel Access Registers
    • 5.2.15 Monitor-Channel Access Registers
• 6 Programming
  • 6.1 C/I Channel Codes
  • 6.2 Monitor Channel Codes
    • 6.2.1 MON-0 Codes
    • 6.2.2 MON-1 Codes
    • 6.2.3 MON-2 Codes
    • 6.2.4 MON-8 Codes
  • 6.3 Predefined EOC Codes
  • 6.4 Example for C/I Channel Programming
  • 6.5 Example for Monitor Channel Programming
  • 6.6 Example for Programming Power Controller Interface
  • 6.7 Examples for Activating Test Loop-Backs
    • 6.7.1 Examples for Analog Loop-Back Control
    • 6.7.2 Examples for Complete Loop-Back #2 Control
    • 6.7.3 Examples for Single Channel Loop-Back #2 Control
  • 6.8 Examples for Activation and Deactivation Control Codes
    • 6.8.1 Complete Activation Initiated by LT
    • 6.8.2 Complete Activation Initiated by TE
    • 6.8.3 Activation with ACT-Bit Status Ignored by Exchange Side
    • 6.8.4 Complete Deactivation
    • 6.8.5 Partial Activation (U Only)
    • 6.8.6 Complete Activation Initiated by LT with U Active
    • 6.8.7 Complete Activation Initiated by TE with U Active
    • 6.8.8 Deactivating S/T-Interface Only
    • 6.8.9 Activation Initiated by LT with Repeater
    • 6.8.10 Activation Initiated by TE with Repeater
    • 6.8.11 Deactivation by Repeater
• 7 Application Hints
  • 7.1 External Circuitry
    • 7.1.1 Power Supply Blocking Recommendation
    • 7.1.2 U-Interface
    • 7.1.3 Oscillator Circuit and Crystal
  • 7.2 Applications with EPIC® on the Line Card (PBX)
  • 7.3 Hints for Repeater Applications
    • 7.3.1 EOC Addressing Management
    • 7.3.2 Single Bits Handling
  • 7.4 Set-ups for Test Modes and System Measurements
    • 7.4.1 Tests in Send Single Pulses Mode
    • 7.4.2 Tests in Data-Through Mode
    • 7.4.3 Tests in Master-Reset Mode
• 8 Electrical Characteristics
  • 8.1 Absolute Maximum Ratings
  • 8.2 Power Supply
  • 8.3 Line Overload Protection
  • 8.4 Power Consumption
  • 8.5 Analog Characteristics
  • 8.6 DC Characteristics
  • 8.7 AC Characteristics
    • 8.7.1 Microprocessor Interface Timing in Parallel Mode
      • 8.7.1.1 Siemens/Intel Bus Mode
      • 8.7.1.2 Motorola Bus Mode
      • 8.7.1.3 Timing Values of the µP interface in Parallel Mode
    • 8.7.2 Serial Microprocessor Interface Timing
    • 8.7.3 IOM®-2 Interface Timing
    • 8.7.4 Power Controller Interface Timing
      • 8.7.4.1 Data Port
      • 8.7.4.2 Interrupt
    • 8.7.5 Undervoltage Detection Timing
    • 8.7.6 Master Clock
      • 8.7.6.1 LT Modes
      • 8.7.6.2 NT Modes
    • 8.7.7 Timing Properties of CLS
    • 8.7.8 Timing Properties of Pin SG in TE Mode
• 9 Package Outlines
• 10 Glossary
• 11 Index