LHF80J05

Rev. 1.27

Handle this document carefully for it contains material protected by international copyright law.

Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.

When using the products covered herein, please observe the conditions written herein and the

precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application

areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).

·Office electronics
·Instrumentation and measuring equipment
·Machine tools
·Audiovisual equipment
·Home appliance
·Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which

demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.

·Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment

·Mainframe computers
·Traffic control systems
·Gas leak detectors and automatic cutoff devices
·Rescue and security equipment
·Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands

extremely high performance in terms of functionality, reliability, or accuracy.

·Aerospace equipment
·Communications equipment for trunk lines
·Control equipment for the nuclear power industry
·Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three

Paragraphs to a sales representative of the company.

Please direct all queries regarding the products covered herein to a sales representative of the

company.

sharp

LHF80J05

Rev. 1.27

CONTENTS

PAGE

1 INTRODUCTION.............................................................. 3

1.1 Features ........................................................................ 3

1.2 Product Overview......................................................... 3

1.3 Product Description ...................................................... 4

1.3.1 Package Pinout ....................................................... 4

1.3.2 Block Organization................................................. 4

2 PRINCIPLES OF OPERATION........................................ 7

2.1 Data Protection ............................................................. 8

3 BUS OPERATION ............................................................ 8

3.1 Read.............................................................................. 8

3.2 Output Disable.............................................................. 8

3.3 Standby......................................................................... 8

3.4 Reset............................................................................. 8

3.5 Read Identifier Codes................................................... 9

3.6 OTP(One Time Program) Block .................................. 9

3.7 Write........................................................................... 10

4 COMMAND DEFINITIONS........................................... 10

4.1 Read Array Command................................................ 12

4.2 Read Identifier Codes Command ............................... 12

4.3 Read Status Register Command ................................. 12

4.4 Clear Status Register Command................................. 12

4.5 Block Erase Command ............................................... 13

4.6 Full Chip Erase Command ......................................... 13

4.7 Word/Byte Write Command....................................... 13

4.8 Block Erase Suspend Command ................................ 14

4.9 Word/Byte Write Suspend Command ........................ 14

4.10 Set Block and Permanent Lock-Bit Commands ....... 15

4.11 Clear Block Lock-Bits Command ............................ 15

4.12 OTP Program Command .......................................... 16

4.13 Block Locking by the WP# ...................................... 16

PAGE

5 DESIGN CONSIDERATIONS ....................................... 27

5.1 Three-Line Output Control ........................................ 27

5.2 RY/BY# and WSM Polling ....................................... 27

5.3 Power Supply Decoupling ......................................... 27

5.4 V

CCW

Trace on Printed Circuit Boards ..................... 27

5.5 V

, V

CCW

, RP# Transitions .................................... 27

5.6 Power-Up/Down Protection....................................... 28

5.7 Power Dissipation ...................................................... 28

5.8 Data Protection Method ............................................. 28

6 ELECTRICAL SPECIFICATIONS ................................ 29

6.1 Absolute Maximum Ratings ...................................... 29

6.2 Operating Conditions ................................................. 29

6.2.1 Capacitance .......................................................... 29

6.2.2 AC Input/Output Test Conditions ........................ 30

6.2.3 DC Characteristics ............................................... 31

6.2.4 AC Characteristics - Read-Only Operations ........ 33

6.2.5 AC Characteristics - Write Operations ................ 36

6.2.6 Alternative CE#-Controlled Writes...................... 38

6.2.7 Reset Operations .................................................. 40

6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and

Lock-Bit Configuration Performance ................. 41

7 PACKAGE AND PACKING SPECIFICATION............ 42

sharp

LHF80J05

Rev. 1.27

LH28F800BJHE-PBTL90

8M-BIT ( 512Kbit ×16 / 1Mbit ×8 )

Boot Block Flash MEMORY

Low Voltage Operation

CCW

=2.7V-3.6V Single Voltage

OTP(One Time Program) Block

3963 word + 4 word Program only array

User-Configurable ×8 or ×16 Operation

High-Performance Read Access Time

90ns(V

=2.7V-3.6V)

Operating Temperature

-40°C to +85°C

Low Power Management

Typ. 2µA (V

=3.0V) Standby Current

Automatic Power Savings Mode Decreases I

CCR

Static Mode
Typ. 120µA (V

=3.0V, T

=+25°C, f=32kHz)

Read Current

Optimized Array Blocking Architecture

Two 4K-word (8K-byte) Boot Blocks
Six 4K-word (8K-byte) Parameter Blocks
Fifteen 32K-word (64K-byte) Main Blocks
Bottom Boot Location

Extended Cycling Capability

Minimum 100,000 Block Erase Cycles

Enhanced Automated Suspend Options

Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read

Enhanced Data Protection Features

Absolute Protection with V

CCW

CCWLK

Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Lockout during Power
Transitions
Block Locking with Command and WP#
Permanent Locking

Automated Block Erase, Full Chip Erase,

Word/Byte Write and Lock-Bit Configuration

Command User Interface (CUI)
Status Register (SR)

SRAM-Compatible Write Interface

Industry-Standard Packaging

48-Lead TSOP

ETOX

TM*

Nonvolatile Flash Technology

CMOS Process (P-type silicon substrate)
Not designed or rated as radiation hardened

The product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications.

The product can operate at V

=2.7V-3.6V and V

CCW

=2.7V-3.6V or 11.7V-12.3V. Its low voltage operation capability

realize battery life and suits for cellular phone application.

Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component
suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code
+ data storage applications.

For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to
DRAM, the product offers four levels of protection: absolute protection with V

CCW

CCWLK

, selective hardware block

locking or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

The product is manufactured on SHARP's 0.25µm ETOX

TM*

process technology. It come in industry-standard package: the

48-lead TSOP, ideal for board constrained applications.

*ETOX is a trademark of Intel Corporation.

sharp

LHF80J05

Rev. 1.27

1 INTRODUCTION

This datasheet contains the product specifications. Section
1 provides a flash memory overview. Sections 2, 3, 4 and
5 describe the memory organization and functionality.
Section 6 covers electrical specifications.

1.1 Features

Key enhancements of the product are:

·Single low voltage operation
·Low power consumption
·Enhanced Suspend Capabilities
·Boot Block Architecture

Please note following:

·V

CCWLK

has been lowered to 1.0V to support 2.7V-

3.6V block erase, full chip erase, word/byte write and
lock-bit configuration operations. The V

CCW

voltage

transitions to GND is recommended for designs that
switch V

CCW

off during read operation.

1.2 Product Overview

The product is a high-performance 8M-bit Boot Block
Flash memory organized as 512K-word of 16 bits or 1M-
byte of 8 bits. The 512K-word/1M-byte of data is arranged
in two 4K-word/8K-byte boot blocks, six 4K-word/8K-
byte parameter blocks and fifteen 32K-word/64K-byte
main blocks which are individually erasable, lockable and
unlockable in-system. The memory map is shown in
Figure 3.

The dedicated V

CCW

pin gives complete data protection

when V

CCW

CCWLK

A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase, full chip erase,
word/byte write and lock-bit configuration operations.

A block erase operation erases one of the device's 32K-
word/64K-byte blocks typically within 1.2s (3V V

, 3V

CCW

), 4K-word/8K-byte blocks typically within 0.6s (3V

, 3V V

CCW

) independent of other blocks. Each block

can be independently erased minimum 100,000 times.
Block erase suspend mode allows system software to
suspend block erase to read or write data from any other
block.

Writing memory data is performed in word/byte
increments of the device's 32K-word blocks typically
within 33µs (3V V

, 3V V

CCW

), 64K-byte blocks

typically within 31µs (3V V

, 3V V

CCW

), 4K-word

blocks typically within 36µs (3V V

, 3V V

CCW

), 8K-

byte blocks typically within 32µs (3V V

, 3V V

CCW

Word/byte write suspend mode enables the system to read
data or execute code from any other flash memory array
location.

Individual block locking uses a combination of bits, thirty-
nine block lock-bits, a permanent lock-bit and WP# pin, to
lock and unlock blocks. Block lock-bits gate block erase,
full chip erase and word/byte write operations, while the
permanent lock-bit gates block lock-bit modification and
locked block alternation. Lock-bit configuration
operations (Set Block Lock-Bit, Set Permanent Lock-Bit
and Clear Block Lock-Bits commands) set and cleared
lock-bits.

The status register indicates when the WSM's block erase,
full chip erase, word/byte write or lock-bit configuration
operation is finished.

The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/BY#-high Z
indicates that the WSM is ready for a new command,
block erase is suspended (and

word/byte write is

inactive), word/byte write is suspended, or the device is in
reset mode.

sharp

LHF80J05

Rev. 1.27

The access time is 90ns (t

AVQV

) over the operating

temperature range (-40°C to +85°C) and V

supply

voltage range of 2.7V-3.6V.

The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I

CCR

current is 2µA (CMOS) at 3.0V V

When CE# and RP# pins are at V

, the I

CMOS

standby mode is enabled. When the RP# pin is at GND,
reset mode is enabled which minimizes power
consumption and provides write protection. A reset time
(t

PHQV

) is required from RP# switching high until outputs

are valid. Likewise, the device has a wake time (t

PHEL

)

from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.

Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".

·Program "0" for the bit in which you want to change

data from "1" to "0".

·Program "1" for the bit which has already been

programmed "0".

For example, changing data from "10111101" to
"10111100" requires "11111110" programming.

1.3 Product Description

1.3.1 Package Pinout

The product is available in 48-lead TSOP package (see
Figure 2).

1.3.2 Block Organization

This product features an asymmetrically-blocked
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks, see
the memory map in Figure 3.

Boot Blocks: The boot block is intended to replace a
dedicated boot PROM in a microprocessor or
microcontroller-based system. This boot block 4K words
(4,096words) features hardware controllable write-
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
block is controlled using a combination of the V

CCW

, RP#,

WP# pins and block lock-bit.

Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small parameters that would normally require an
EEPROM. By using software techniques, the word-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 4K
words (4,096 words) each. The protection of the parameter
block is controlled using a combination of the V

CCW

, RP#

and block lock-bit.

Main Blocks: The reminder is divided into main blocks for
data or code storage. Each 8M-bit device contains fifteen
32K words (32,768 words) blocks. The protection of the
main block is controlled using a combination of the
V

CCW

, RP# and block lock-bit.

sharp

Output

Buffer

Input

Buffer

Input

Buffer

Decoder

Identifier

Output

Multiplexer

Status

Data

Comparator

Y-Gating

Data

Command

User

Interface

I/O

Logic

Write

State

Machine

Program/Erase

Voltage Switch

BYTE#

CE#

WE#

OE#

RP#

RY/BY#

CCW

GND

Decoder

Address

Latch

Address
Counter

Main Block 0

Main Block 1

Main Block 14

OTP Block

32K-Word

(64K-Byte)

Main Blocks

×15

Boot Block 0

Boot Block 1

Parameter Block 0

Parameter Block 1

Parameter Block 2

Parameter Block 3

Parameter Block 4

Parameter Block 5

-1

-A

-DQ

WP#

Main Block 13

48-LEAD TSOP

STANDARD PINOUT

12mm x 20mm

TOP VIEW

CE#

CCW

RP#

RY/BY#

WE#

OE#

GND

21
22
23
24

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17

-1

WP#

BYTE#

LHF80J05

Rev. 1.27

Figure 1. Block Diagram

Figure 2. TSOP 48-Lead Pinout

sharp

LHF80J05

Rev. 1.27

Table 1. Pin Descriptions

Symbol

Type

Name and Function

-1

-A

INPUT

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A

-1

: Lower address input while BYTE# is V

. A

-1

pin changes DQ

pin while BYTE# is V

-A

: Main Block Address.

-A

: Boot and Parameter Block Address.

-DQ

INPUT/

OUTPUT

DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data
during memory array, status register and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle. DQ

-DQ

pins are not used while byte mode (BYTE#=V

). Then, DQ

changes A

-1

address input.

CE#

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.

RP#

INPUT

RESET: Resets the device internal automation. RP#-high enables normal operation. When driven
low, RP# inhibits write operations which provides data protection during power transitions. Exit
from reset mode sets the device to read array mode. RP# must be V

during power-up.

OE#

INPUT

OUTPUT ENABLE: Gates the device's outputs during a read cycle.

WE#

INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.

WP#

INPUT

WRITE PROTECT: When WP# is V

, boot blocks cannot be written or erased. When WP# is

, locked boot blocks can not be written or erased. WP# is not affected parameter and main

blocks.

BYTE#

INPUT

BYTE ENABLE: BYTE# V

places device in byte mode (×8). All data is then input or output on

0-7

, and DQ

8-15

float. BYTE# V

places the device in word mode (×16), and turns off the A

-1

input buffer.

RY/BY#

OPEN

DRAIN

OUTPUT

READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
internal operation (block erase, full chip erase, word/byte write or lock-bit configuration).
RY/BY#-high Z indicates that the WSM is ready for new commands, block erase is suspended,
and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode.

CCW

SUPPLY

BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or
configuring lock-bits. With V

CCW

CCWLK

, memory contents cannot be altered. Block erase, full

chip erase, word/byte write and lock-bit configuration with an invalid V

CCW

(see 6.2.3 DC

Characteristics) produce spurious results and should not be attempted. Applying 12V±0.3V to
V

CCW

during erase/write can only be done for a maximum of 1000 cycles on each block. V

CCW

may be connected to 12V±0.3V for a total of 80 hours maximum.

SUPPLY

DEVICE POWER SUPPLY: Do not float any power pins. With V

LKO

, all write attempts to

the flash memory are inhibited. Device operations at invalid V

voltage (see 6.2.3 DC

Characteristics) produce spurious results and should not be attempted.

GND

SUPPLY

GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internal connected; it may be driven or floated.

sharp

32KW/64KB Main Block 14

32KW/64KB Main Block 5

32KW/64KB Main Block 4

32KW/64KB Main Block 3

32KW/64KB Main Block 2

32KW/64KB Main Block 1

32KW/64KB Main Block 0

4KW/8KB Boot Block 1

4KW/8KB Boot Block 0

4KW/8KB Parameter Block 5

4KW/8KB Parameter Block 4

4KW/8KB Parameter Block 3

4KW/8KB Parameter Block 2

4KW/8KB Parameter Block 1

4KW/8KB Parameter Block 0

32KW/64KB Main Block 12

32KW/64KB Main Block 10

32KW/64KB Main Block 11

32KW/64KB Main Block 13

32KW/64KB Main Block 9

32KW/64KB Main Block 8

32KW/64KB Main Block 7

32KW/64KB Main Block 6

7FFFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

00000

00FFF

07000

06000

06FFF

05000

05FFF

04000

04FFF

03000

03FFF

02000

02FFF

01000

01FFF

0FFFFF
0F0000
0EFFFF

0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF

0A0000
09FFFF
090000
08FFFF
080000
07FFFF

070000
06FFFF
060000
05FFFF
050000
04FFFF

040000

03FFFF
030000
02FFFF
020000

01FFFF

010000
00FFFF

000000

001FFF

00E000

00C000

00DFFF

00A000

00BFFF

008000

009FFF

006000

007FFF

004000

005FFF

002000

003FFF

Bottom Boot

-A

]

-A

-1

]

LHF80J05

Rev. 1.27

2 PRINCIPLES OF OPERATION

The product includes an on-chip WSM to manage block
erase, full chip erase, word/byte write and lock-bit
configuration functions. It allows for: fixed power supplies
during block erase, full chip erase, word/byte write and
lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.

After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.

Status register and identifier codes can be accessed
through the CUI independent of the V

CCW

voltage. High

voltage on V

CCW

enables successful block erase, full chip

erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents-block
erase, full chip erase, word/byte write, lock-bit
configuration, status and identifier codes-are accessed via
the CUI and verified through the status register.

Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.

Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.

Figure 3. Memory Map

sharp

LHF80J05

Rev. 1.27

2.1 Data Protection

When V

CCW

CCWLK

, memory contents cannot be

altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to V

CCW

. All write

functions are disabled when V

is below the write

lockout voltage V

LKO

or when RP# is at V

. The device's

block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.

3 BUS OPERATION

The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier codes
or status register independent of the V

CCW

voltage. RP#

can be at V

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode, the device automatically
resets to read array mode. Six control pins dictate the data
flow in and out of the component: CE#, OE#, BYTE#,
WE#, RP# and WP#. CE# and OE# must be driven active
to obtain data at the outputs. CE# is the device selection
control, and when active enables the selected memory
device. OE# is the data output (DQ

-DQ

) control and

when active drives the selected memory data onto the I/O
bus. BYTE# is the device I/O interface mode control.
WE# must be at V

, RP# must be at V

, and BYTE#

and WP# must be at V

or V

. Figure 16, 17 illustrates

read cycle.

3.2 Output Disable

With OE# at a logic-high level (V

), the device outputs

are disabled. Output pins (DQ

-DQ

) are placed in a

high-impedance state.

3.3 Standby

CE# at a logic-high level (V

) places the device in

standby mode which substantially reduces device power
consumption. DQ

-DQ

outputs are placed in a high-

impedance state independent of OE#. If deselected during
block erase, full chip erase, word/byte write or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.

3.4 Reset

RP# at V

initiates the reset mode.

In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time t

PHQV

is required after return from reset

mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.

During block erase, full chip erase, word/byte write or
lock-bit configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
t

PHWL

is required after RP# goes to logic-high (V

)

before another command can be written.

As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase, full chip erase, word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing status
information instead of array data. SHARP's flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.

sharp

(Parameter Blocks 1 through 4)

06FFF

03000

-A

]

00FFF

00004

00002

00000

01FFF

01002

01001

01000

Device Code

Manufacturer Code

Boot Block 1

Reserved for Future Implementation

Boot Block 0

Reserved for Future Implementation

Boot Block 1 Lock Configuration Code

Boot Block 0 Lock Configuration Code

01003

00003

00001

Permanent Lock Configuration Code

02FFF

02002

02001

02000

02003

Parameter Block 0

Reserved for Future Implementation

Parameter Block 0 Lock Configuration Code

07FFF

07002

07001

07000

07003

Parameter Block 5

Reserved for Future Implementation

Parameter Block 5 Lock Configuration Code

(Main Blocks 1 through 13)

77FFF

10000

0FFFF

08002

08001

08000

08003

Main Block 0

Reserved for Future Implementation

Main Block 0 Lock Configuration Code

7FFFF

78002

78001

78000

78003

Main Block 14

Reserved for Future Implementation

Main Block 14 Lock Configuration Code

Bottom Boot

Reserved for Future Implementation

0007F

00080

OTP Block

0DFFF

06000

-A

-1

]

01FFF

00008

00000

03FFF

02004
02003

02000

02006

05FFF

04004
04003

04000

04006

0FFFF

0E004
0E003

0E000

0E006

EFFFF

20000

1FFFF

10004
10003

10000

01006

FFFFF

F0004

F0003

F0000

F0006

000FF

00100

00005

00001

00007

00003

00002

00004

00006

02005

04005

0E005

10005

F0005

Customer Program Area

00085

00FFF

-A

]

Factory Program Area

OTP Lock

00081

00080

00084

Customer Program Area Lock(Bit 1)

Factory Program Area Lock(Bit 0)

0010A

01FFF

00102

00100

00109

-A

-1

]

LHF80J05

Rev. 1.27

3.5 Read Identifier Codes

The read identifier codes operation outputs the
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.

Figure 4. Device Identifier Code Memory Map

3.6 OTP(One Time Program) Block

The OTP block is a special block that can not be erased.
The block is divided into two parts. One is a factory
program area where a unique number can be written
according to customer requirements in SHARP factory.
This factory program area is "READ ONLY" (Already
locked). The other is a customer program area that can be
used by customers. This customer program area can be
locked. After locking, this customer program area is
protected permanently.

The OTP block is read in Configuration Read Mode by
writing Read Identifier Codes command(90H). To return
to Read Array Mode, write Read Array command(FFH).

The OTP block is programmed by writing OTP Program
command(C0H). First write OTP Program command and
then write data with address to the device (See Figure 5).
If OTP program is failed, SR.4(WORD/BYTE WRITE
AND SET LOCK-BIT STATUS) bit is set to "1". And if
this OTP block is locked, SR.1(DEVICE PROTECT
STATUS) bit is set to "1" too.

The OTP block is also locked by writing OTP Program
command(C0H). First write OTP Program command and
then write data "FFFDH" with address "80H" to the
device. Address "80H" of OTP block is OTP lock
information. Bit 0 of address "80H"

means factory

program area lock status("1" is "NOT LOCKED", "0" is
"LOCKED"). Bit 1 of address "80H" means customer
program area lock status. The OTP lock information can
not be cleared, after once it is set.

Figure 5. OTP Block Address Map

sharp

LHF80J05

Rev. 1.27

3.7 Write

Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V

=2.7V-3.6V and

CCW

CCWH1/2

, the CUI additionally controls block

erase, full chip erase, word/byte write and lock-bit
configuration.

The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 18 and 19 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the V

CCW

voltage

CCWLK

, read operations from

the status register, identifier codes, or blocks are enabled.
Placing V

CCWH1/2

on V

CCW

enables successful block

erase, full chip erase, word/byte write and lock-bit
configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.

Table 2.1. Bus Operations (BYTE#=V

)

(1,2)

Mode

Notes

RP#

CE#

OE#

WE#

Address

CCW

0-15

RY/BY#

(3)

Read

OUT

Output Disable

High Z

Standby

High Z

Reset

High Z

Read Identifier Codes

See

Figure 4, 5

Note 5

High Z

Write

6,7,8

Table 2.2. Bus Operations (BYTE#=V

)

(1,2)

Mode

Notes

RP#

CE#

OE#

WE#

Address

CCW

0-7

RY/BY#

(3)

Read

OUT

Output Disable

High Z

Standby

High Z

Reset

High Z

Read Identifier Codes

See

Figure 4, 5

Note 5

High Z

Write

6,7,8

NOTES:
1. Refer to DC Characteristics. When V

CCW

CCWLK

, memory contents can be read, but not altered.

2. X can be V

or V

for control pins and addresses, and V

CCWLK

or V

CCWH1/2

for V

CCW

. See DC Characteristics for

CCWLK

voltages.

3. RY/BY# is V

when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration

algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.

4. RP# at GND±0.2V ensures the lowest power consumption.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed

when V

CCW

CCWH1/2

and V

=2.7V-3.6V.

7. Refer to Table 3 for valid D

during a write operation.

8. Never hold OE# low and WE# low at the same timing.

sharp

LHF80J05

Rev. 1.27

Table 3. Command Definitions

(10)

Bus Cycles

First Bus Cycle

Second Bus Cycle

Command

Req'd.

Notes

Oper

(1)

Addr

(2)

Data

(3)

Oper

(1)

Addr

(2)

Data

(3)

Read Array/Reset

Write

FFH

Read Identifier Codes

Write

90H

Read

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Block Erase

Write

20H

Write

D0H

Full Chip Erase

Write

30H

Write

D0H

Word/Byte Write

5,6

Write

40H or

10H

Write

Block Erase and Word/Byte
Write Suspend

Write

B0H

Block Erase and Word/Byte
Write Resume

Write

D0H

Set Block Lock-Bit

Write

60H

Write

01H

Clear Block Lock-Bits

7,8

Write

60H

Write

D0H

Set Permanent Lock-Bit

Write

60H

Write

F1H

OTP Program

Write

C0H

Write

NOTES:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X=Any valid address within the device.

IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
OA=Address of OTP block to be written: see Figure 5.

3. ID=Data read from identifier codes.

SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
OD=Data to be written at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and

permanent lock configuration codes. See Section 4.2 for read identifier code data.

5. If WP# is V

, boot blocks are locked without block lock-bits state. If WP# is V

, boot blocks are locked by block lock-

bits. The parameter and main blocks are locked by block lock-bits without WP# state.

6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

sharp

LHF80J05

Rev. 1.27

4.1 Read Array Command

Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This
operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase, full chip erase, word/byte write or
lock-bit configuration the device will not recognize the
Read Array command until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend or Word/Byte Write Suspend command. The
Read Array command functions independently of the
V

CCW

voltage and RP# can be V

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer, device, block lock configuration
and permanent lock configuration codes (see Table 4 for
identifier code values). To terminate the operation, write
another valid command. Like the Read Array command,
the Read Identifier Codes command functions
independently of the V

CCW

voltage and RP# can be V

Following the Read Identifier Codes command, the
following information can be read:

Table 4. Identifier Codes

Code

Address

(2)

-A

]

Data

(3)

[DQ

-DQ

]

Manufacture Code

00000H

B0H

Device Code

00001H

EDH

Block Lock Configuration

(1)

·Block is Unlocked

·Block is Locked

·Reserved for Future Use

1-7

Permanent Lock Configuration

00003H

·Device is Unlocked

·Device is Locked

·Reserved for Future Use

1-7

NOTE:
1. BA selects the specific block lock configuration code

to be read. See Figure 4 for the device identifier code
memory map.

2. A

-1

don't care in byte mode.

3. DQ

-DQ

outputs 00H in word mode.

4.3 Read Status Register Command

The status register may be read to determine when a block
erase, full chip erase, word/byte write or lock-bit
configuration is complete and whether the operation
completed successfully. It may be read at any time by
writing the Read Status Register command. After writing
this command, all subsequent read operations output data
from the status register until another valid command is
written. The status register contents are latched on the
falling edge of OE# or CE#, whichever occurs. OE# or
CE# must toggle to V

before further reads to update the

status register latch. The Read Status Register command
functions independently of the V

CCW

voltage. RP# can be

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 6). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.

To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V

CCW

Voltage. RP# can be V

. This

command is not functional during block erase or
word/byte write suspend modes.

sharp

LHF80J05

Rev. 1.27

4.5 Block Erase Command

Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH). Block preconditioning, erase, and verify
are handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status register
data when read (see Figure 6). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.

This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V

=2.7V-3.6V and V

CCW

CCWH1/2

. In the absence of

this high voltage, block contents are protected against
erasure. If block erase is attempted while V

CCW

CCWLK

SR.3 and SR.5 will be set to "1". Successful block erase
requires for boot blocks that WP# is V

and the

corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding
block lock-bit. If block erase is attempted when the
excepting above conditions, SR.1 and SR.5 will be set to
"1".

4.6 Full Chip Erase Command

This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (D0H).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip
erase sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU can
detect full chip erase completion by analyzing the output
data of the RY/BY# pin or status register bit SR.7.

When the full chip erase is complete, status register bit
SR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read

status register mode until a new command is issued. If
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
block. Full chip erase can not be suspended.

This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to "1". Also, reliable full chip erasure can only occur
when V

=2.7V-3.6V and V

CCW

CCWH1/2

. In the

absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
V

CCW

CCWLK

, SR.3 and SR.5 will be set to "1".

Successful full chip erase requires for boot blocks that
WP# is V

and the corresponding block lock-bit be

cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked, SR.1 and SR.5 will be set to "1".

4.7 Word/Byte Write Command

Word/Byte write is executed by a two-cycle command
sequence. Word/Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 8). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.

When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.

Reliable word/byte writes can only occur when
V

=2.7V-3.6V and V

CCW

CCWH1/2

. In the absence of

this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V

CCW

CCWLK

, status register bits SR.3 and SR.4 will be

set to "1". Successful word/byte write requires for boot
blocks that WP# is V

and the corresponding block lock-

bit be cleared. In parameter and main blocks case, it must
be cleared the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR.1 and SR.4 will be set to "1".

sharp

LHF80J05

Rev. 1.27

4.8 Block Erase Suspend Command

The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
t

WHRZ2

defines the block erase suspend latency.

When Block Erase Suspend command write to the CUI, if
block erase was finished, the device places read array
mode. Therefore, after Block Erase Suspend command
write to the CUI, Read Status Register command (70H)
has to write to CUI, then status register bit SR.6 should be
checked for places the device in suspend mode.

At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.9), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V

. However,

SR.6 will remain "1" to indicate block erase suspend
status.

The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to V

. After

the Erase Resume command is written, the device
automatically outputs status register data when read (see
Figure 9). V

CCW

must remain at V

CCWH1/2

(the same

CCW

level used for block erase) while block erase is

suspended. RP# must also remain at V

. WP# must also

remain at V

or V

(the same WP# level used for block

erase). Block erase cannot resume until word/byte write
operations initiated during block erase suspend have
completed.

If the time between writing the Block Erase Resume
command and writing the Block Erase Suspend command
is shorter than t

ERES

and both commands are written

repeatedly, a longer time is required than standard block
erase until the completion of the operation.

4.9 Word/Byte Write Suspend Command

The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the Word/Byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). RY/BY# will also transition to
High Z. Specification t

WHRZ1

defines the word/byte write

suspend latency.

When Word/Byte Write Suspend command write to the
CUI, if word/byte write was finished, the device places
read array mode. Therefore, after Word/Byte Write
Suspend command write to the CUI, Read Status Register
command (70H) has to write to CUI, then status register
bit SR.2 should be checked for places the device in
suspend mode.

At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V

. After the Word/Byte Write

Resume command is written, the device automatically
outputs status register data when read (see Figure 10).
V

CCW

must remain at V

CCWH1/2

(the same V

CCW

level

used for word/byte write) while in word/byte write
suspend mode. RP# must also remain at V

. WP# must

also remain at V

or V

(the same WP# level used for

word/byte write).

If the time between writing the Word/Byte Write Resume
command and writing the Word/Byte Write Suspend
command is short and both commands are written
repeatedly, a longer time is required than standard
word/byte write until the completion of the operation.

sharp

LHF80J05

Rev. 1.27

4.10 Set Block and Permanent Lock-Bit

Commands

A flexible block locking and unlocking scheme is enabled
via a combination of block lock-bits, a permanent lock-bit
and WP# pin. The block lock-bits and WP# pin gates
program and erase operations while the permanent lock-bit
gates block-lock bit modification. With the permanent
lock-bit not set, individual block lock-bits can be set using
the Set Block Lock-Bit command. The Set Permanent
Lock-Bit command, sets the permanent lock-bit. After the
permanent lock-bit is set, block lock-bits and locked block
contents cannot altered. See Table 5 for a summary of
hardware and software write protection options.

Set block lock-bit and permanent lock-bit are executed by
a two-cycle command sequence. The set block or
permanent lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set permanent lock-bit confirm (and any
device address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read (see
Figure 11). The CPU can detect the completion of the set
lock-bit event by analyzing the RY/BY# pin output or
status register bit SR.7.

When the set lock-bit operation is complete, status register
bit SR.4 should be checked. If an error is detected, the
status register should be cleared. The CUI will remain in
read status register mode until a new command is issued.

This two-step sequence of set-up followed by execution
ensures that lock-bits are not accidentally set. An invalid
Set Block or Permanent Lock-Bit command will result in
status register bits SR.4 and SR.5 being set to "1". Also,
reliable operations occur only when V

=2.7V-3.6V and

CCW

CCWH1/2

. In the absence of this high voltage,

lock-bit contents are protected against alteration.

A successful set block lock-bit operation requires that the
permanent lock-bit be cleared. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set to "1"
and the operation will fail.

4.11 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear
Block Lock-Bits command. With the permanent lock-bit
not set, block lock-bits can be cleared using only the Clear
Block Lock-Bits command. If the permanent lock-bit is
set, block lock-bits cannot cleared. See Table 5 for a
summary of hardware and software write protection
options.

Clear block lock-bits operation is executed by a two-cycle
command sequence. A clear block lock-bits setup is first
written. After the command is written, the device
automatically outputs status register data when read (see
Figure 12). The CPU can detect completion of the clear
block lock-bits event by analyzing the RY/BY# Pin output
or status register bit SR.7.

When the operation is complete, status register bit SR.5
should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until another
command is issued.

This two-step sequence of set-up followed by execution
ensures that block lock-bits are not accidentally cleared.
An invalid Clear Block Lock-Bits command sequence will
result in status register bits SR.4 and SR.5 being set to "1".
Also, a reliable clear block lock-bits operation can only
occur when V

=2.7V-3.6V and V

CCW

CCWH1/2

. If a

clear block lock-bits operation is attempted while
V

CCW

CCWLK

, SR.3 and SR.5 will be set to "1". In the

absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-bit is
not set. If it is attempted with the permanent lock-bit set,
SR.1 and SR.5 will be set to "1" and the operation will
fail.

If a clear block lock-bits operation is aborted due to V

CCW

or V

transitioning out of valid range or RP# active

transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values. Once the permanent lock-bit is set, it cannot be
cleared.

sharp

LHF80J05

Rev. 1.27

4.12 OTP Program Command

OTP program is executed by a two-cycle command
sequence. OTP program command(C0H) is written,
followed by a second write cycle that specifies the address
and data (latched on the rising edge of WE#). The WSM
then takes over, controlling the OTP program and program
verify algorithms internally. After the OTP program
command sequence is completed, the device automatically
outputs status register data when read (see Figure 13). The
CPU can detect the completion of the OTP program by
analyzing the output data of the RY/BY# pin or status
register bit SR.7.

When OTP program is completed, status register bit SR.4
should be checked. If OTP program error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully
program to "0"s. The CUI remains in read status register
mode until it receives other commands.

Reliable OTP program can be executed only when
V

=2.7V-3.6V and V

CCW

CCWH1/2

. In the absence of

this voltage, memory contents are protected against OTP

programs. If OTP program is attempted while
V

CCW

CCWLK

, status register bits SR.3 and SR.4 is set

to "1". If OTP write is attempted when the OTP Lock-bit
is set, SR.1 and SR.4 is set to "1".

4.13 Block Locking by the WP#

This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.

The lockable two boot blocks are locked when WP#=V

;

any program or erase operation to a locked block will
result in an error, which will be reflected in the status
register. For top configuration, the top two boot blocks are
lockable. For the bottom configuration, the bottom two
boot blocks are lockable. If WP# is V

and block lock-

bit is not set, boot block can be programmed or erased
normally (Unless V

CCW

is below V

CCWLK

). WP# is valid

only two boot blocks, other blocks are not affected.

sharp

LHF80J05

Rev. 1.27

Table 5. Write Protection Alternatives

(1)

Operation

CCW

RP#

Permanent

Lock-Bit

Block

Lock-bit

WP#

Effect

Block Erase

CCWLK

All Blocks Locked.

CCWLK

All Blocks Locked.

Word/Byte

2 Boot Blocks Locked.

Write

Block Erase and Word/Byte Write Enabled.

Block Erase and Word/Byte Write Disabled.

Full Chip

CCWLK

All Blocks Locked.

Erase

CCWLK

All Blocks Locked.

All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are NOT Erased.

All Unlocked Blocks are Erased,
Locked Blocks are NOT Erased.

Set Block

CCWLK

Set Block Lock-Bit Disabled.

Lock-Bit

CCWLK

Set Block Lock-Bit Disabled.

Set Block Lock-Bit Enabled.

Set Block Lock-Bit Disabled.

Clear Block

CCWLK

Clear Block Lock-Bits Disabled.

Lock-Bits

CCWLK

Clear Block Lock-Bits Disabled.

Clear Block Lock-Bits Enabled.

Clear Block Lock-Bits Disabled.

Set

CCWLK

Set Permanent Lock-Bit Disabled.

Permanent

CCWLK

Set Permanent Lock-Bit Disabled.

Lock-Bit

Set Permanent Lock-Bit Enabled.

NOTE:
1. X can be V

or V

for RP# and WP#, and "0" or "1" for permanent lock-bit and block lock-bit. See DC Characteristics

for V

CCWLK

voltage.

sharp

LHF80J05

Rev. 1.27

Table 6. Status Register Definition

WSMS

BESS

ECBLBS

WBWSLBS

VCCWS

WBWSS

DPS

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready
0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended
0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS

STATUS (ECBLBS)

1 = Error in Block Erase, Full Chip Erase or Clear Block

Lock-Bits

0 = Successful Block Erase, Full Chip Erase or Clear

Block Lock-Bits

SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT

STATUS (WBWSLBS)

1 = Error in Word/Byte Write or Set Block/Permanent

Lock-Bit

0 = Successful Word/Byte Write or Set Block/Permanent

Lock-Bit

SR.3 = V

CCW

STATUS (VCCWS)

1 = V

CCW

Low Detect, Operation Abort

0 = V

CCW

SR.2 = WORD/BYTE WRITE SUSPEND STATUS

(WBWSS)

1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#

Lock Detected, Operation Abort

0 = Unlock

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Check RY/BY# or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".

If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.

SR.3 does not provide a continuous indication of V

CCW

level. The WSM interrogates and indicates the V

CCW

level

only after Block Erase, Full Chip Erase, Word/Byte Write or
Lock-Bit Configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when
V

CCW

CCWH1/2

SR.1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or WP# is V

. Reading

the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.

SR.0 is reserved for future use and should be masked out
when polling the status register.

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Erase Setup

Erase

Confirm

Data=20H

Addr=X

Data=D0H

Addr=Within Block to be Erased

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent block erasures.

Full status check can be done after each block erase or after a sequence of

block erasures.

Write FFH after the last operation to place device in read array mode.

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1=Command Sequence Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases

where multiple blocks are erased before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.5

1=Block Erase Error

Standby

Check SR.3

1=V

CCW

Error Detect

Check SR.1

1=Device Protect Detect

Start

Write 20H

Write D0H,

Block Address

Read Status

SR.7=

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Device Protect Error

Command Sequence

Error

Block Erase Error

SR.1=

SR.4,5=

SR.5=

Block Erase Successful

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Write 70H

LHF80J05

Rev. 1.27

Figure 6. Automated Block Erase Flowchart

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Full Chip Erase

Confirm

Data=30H

Addr=X

Data=D0H

Addr=X

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Full status check can be done after each full chip erase.

Write FFH after the last operation to place device in read array mode.

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1=Command Sequence Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases

where multiple blocks are erased before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.5

1=Full Chip Erase Error

Standby

Check SR.3

1=V

CCW

Error Detect

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Command Sequence

Error

Full Chip Erase Error

SR.4,5=

SR.5=

Full Chip Erase

Successful

Start

Write 30H

Write D0H

Read Status

SR.7=

Full Status

Check if Desired

Full Chip Erase

Complete

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Full Chip Erase

Setup

Device Protect Error

SR.1=

Standby

Check SR.1

1=Device Protect Detect

(All Blocks are locked)

LHF80J05

Rev. 1.27

Figure 7. Automated Full Chip Erase Flowchart

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Setup Word/Byte Write

Word/Byte Write

Data=40H or 10H

Addr=X

Data=Data to Be Written

Addr=Location to Be Written

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent word/byte writes.

SR full status check can be done after each word/byte write, or after a sequence of

word/byte writes.

Write FFH after the last word/byte write operation to place device in read array mode.

Bus

Operation

Command

Comments

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases

where multiple locations are written before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.4

1=Data Write Error

Standby

Check SR.3

1=V

CCW

Error Detect

Check SR.1

1=Device Protect Detect

Start

Write 40H or 10H

Write Word/Byte

Data and Address

Read

Status Register

SR.7=

Suspend

Word/Byte

Write

Yes

Suspend Word/Byte

Write Loop

Full Status

Check if Desired

Word/Byte Write

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Device Protect Error

Word/Byte Write Error

SR.1=

SR.4=

Word/Byte Write Successful

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

LHF80J05

Rev. 1.27

Figure 8. Automated Word/Byte Write Flowchart

sharp

Start

Write 60H

Write 01H/F1H,

Block/Device Address

Read

Status Register

SR.7=

Full Status

Check if Desired

Set Lock-Bit

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Device Protect Error

Command Sequence

Error

Set Lock-Bit Error

SR.1=

SR.4,5=

SR.4=

Set Lock-Bit Successful

Bus

Operation

Command

Comments

Write

Read

Standby

Data=60H

Addr=X

Data=01H(Block),

F1H(Permanent)

Addr=Block Address(Block),

Device Address(Permanent)

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent lock-bit set operations.

Full status check can be done after each lock-bit set operation or after a sequence of

lock-bit set operations.

Write FFH after the last lock-bit set operation to place device in read array mode.

Set

Block/Permanent

Lock-Bit Setup

Set

Block or Permanent

Lock-Bit Confirm

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1=Command Sequence Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases

where multiple lock-bits are set before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.4

1=Set Lock-Bit Error

Standby

Check SR.3

1=V

CCW

Error Detect

Check SR.1

1=Device Protect Detect

Permanent Lock-Bit is Set

(Set Block Lock-Bit Operation)

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

LHF80J05

Rev. 1.27

Figure 11. Set Block and Permanent Lock-Bit Flowchart

sharp

Start

Write 60H

Write D0H

Read

Status Register

SR.7=

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Device Protect Error

Command Sequence

Error

Clear Block Lock-Bits

Error

SR.1=

SR.4,5=

SR.5=

Clear Block Lock-Bits

Successful

Bus

Operation

Command

Comments

Write

Read

Standby

Data=60H

Addr=X

Data=D0H

Addr=X

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Write FFH after the Clear Block Lock-Bits operation to place device in read array mode.

Clear Block

Lock-Bits Setup

Clear Block

Lock-Bits Confirm

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1=Command Sequence Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.5

1=Clear Block Lock-Bits Error

Standby

Check SR.3

1=V

CCW

Error Detect

Check SR.1

1=Device Protect Detect

Permanent Lock-Bit is Set

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

LHF80J05

Rev. 1.27

Figure 12. Clear Block Lock-Bits Flowchart

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Setup OTP Program

OTP Program

Data=C0H

Addr=X

Data=Data to Be Written

Addr=Location to Be Written

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent OTP programs.

SR full status check can be done after each OTP program, or after a sequence of

OTP programs.

Write FFH after the last OTP program operation to place device in read array mode.

Bus

Operation

Command

Comments

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases

where multiple locations are written before full status is checked.

If error is detected, clear the Status Register before attempting retry or other error recovery.

Check SR.4

1=Data Write Error

Standby

Check SR.3

1=V

CCW

Error Detect

Check SR.1

1=Device Protect Detect

Start

Write C0H

Write Data and Address

Read

Status Register

SR.7=

Full Status

Check if Desired

OTP Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

CCW

Range Error

Device Protect Error

OTP Program Error

SR.1=

SR.4=

OTP Program Successful

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

LHF80J05

Rev. 1.27

Figure 13. Automated OTP Program Flowchart

sharp

LHF80J05

Rev. 1.27

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:

a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not

occur.

To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system's READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.

5.2 RY/BY# and WSM Polling

RY/BY# is an open drain output that should be connected
to V

by a pull up resistor to provides a hardware method

of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
bit configuration commands and returns to V

(while

RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.

RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs' capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V

and GND and between its

CCW

and GND. These high-frequency, low inductance

capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array's power
supply connection between V

and GND. The bulk

capacitor will overcome voltage slumps caused by PC
board trace inductance.

5.4 V

CCW

Trace on Printed Circuit Boards

Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V

CCW

Power supply trace. The V

CCW

supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V

power bus. Adequate

CCW

supply traces and decoupling will decrease V

CCW

voltage spikes and overshoots.

5.5 V

, V

CCW

, RP# Transitions

Block erase, full chip erase, word/byte write and lock-bit
configuration are not guaranteed if V

CCW

falls outside of a

valid V

CCWH1/2

range, V

falls outside of a valid 2.7V-

3.6V range, or RP#

. If V

CCW

error is detected, status

during block erase, full chip erase, word/byte write

or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V

clear the status register.

The CUI latches commands issued by system software and
is not altered by V

CCW

or CE# transitions or WSM

actions. Its state is read array mode upon power-up, after
exit from reset mode or after V

transitions below V

LKO

sharp

LHF80J05

Rev. 1.27

5.6 Power-Up/Down Protection

The device is designed to offer protection against
accidental block erase, full chip erase, word/byte write or
lock-bit configuration during power transitions. Upon
power-up, the device is indifferent as to which power
supply (V

CCW

or V

) powers-up first. Internal circuitry

resets the CUI to read array mode at power-up.

A system designer must guard against spurious writes for
V

voltages above V

LKO

when V

CCW

is active. Since

both WE# and CE# must be low for a command write,
driving either to V

will inhibit writes. The CUI's two-

step command sequence architecture provides added level
of protection against data alteration.

In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP#=V

regardless of its control inputs state.

5.7 Power Dissipation

When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory's nonvolatility increases usable
battery life because data is retained when system power is
removed.

5.8 Data Protection Method

Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands, causing undesired memory updating. To
protect the data stored in the flash memory against
unwanted overwriting, systems operating with the flash
memory should have the following write protect designs,
as appropriate:

1) Protecting data in specific block

When a lock bit is set, the corresponding block (includes
the 2 boot blocks) is protected against overwriting. By
setting a WP# to low, only the 2 boot blocks can be
protected against overwriting. By using this feature, the
flash memory space can be divided into the program
section (locked section) and data section (unlocked
section). The permanent lock bit can be used to prevent
false block bit setting. For further information on
setting/resetting lock-bit, refer to the specification. (See
chapter 4.10 and 4.11.)

2) Data protection through V

CCW

When the level of V

CCW

is lower than V

CCWLK

(lockout

voltage), write operation on the flash memory is disabled.
All blocks are locked and the data in the blocks are
completely write protected. For the lockout voltage, refer
to the specification. (See chapter 6.2.3.)

3) Data protection through RP#

When the RP# is kept low during read mode, the flash
memory will be reset mode, then write protecting all
blocks. When the RP# is kept low during power up and
power down sequence such as voltage transition, write
operation on the flash memory is disabled, write
protecting all blocks. For the details of RP# control, refer
to the specification. (See chapter 5.6 and 6.2.7.)

sharp

LHF80J05

Rev. 1.27

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Block Erase,
Full Chip Erase, Word/Byte Write
and Lock-Bit Configuration .............-40°C to +85°C

(1)

Storage Temperature

During under Bias ............................... -40°C to +85°C
During non Bias ................................ -65°C to +125°C

Voltage On Any Pin

(except V

and V

CCW

) ........... -0.5V to V

+0.5V

(2)

Supply Voltage................................ -0.2V to +4.6V

(2)

CCW

Supply Voltage......................... -0.2V to +13.0V

(2,3)

Output Short Circuit Current................................100mA

(4)

*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.

NOTES:
1. Operating temperature is for extended temperature

product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V

and V

CCW

pins. During transitions,

this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins are
V

+0.5V which, during transitions, may overshoot to

+2.0V for periods <20ns.

3. Maximum DC voltage on V

CCW

may overshoot to

+13.0V for periods <20ns. Applying 12V±0.3V to
V

CCW

during erase/write can only be done for a

maximum of 1000 cycles on each block. V

CCW

may be

connected to 12V±0.3V for a total of 80 hours
maximum.

4. Output shorted for no more than one second. No more

than one output shorted at a time.

6.2 Operating Conditions

Temperature and V

Operating Conditions

Symbol

Parameter

Min.

Max.

Unit

Test Condition

Operating Temperature

-40

+85

°C

Ambient Temperature

Supply Voltage (2.7V-3.6V)

2.7

3.6

6.2.1 Capacitance

(1)

=+25°C, f=1MHz

Symbol

Parameter

Typ.

Max.

Unit

Condition

Input Capacitance

=0.0V

OUT

Output Capacitance

OUT

=0.0V

NOTE:
1. Sampled, not 100% tested.

sharp

LHF80J05

Rev. 1.27

6.2.3 DC Characteristics

DC Characteristics

=2.7V-3.6V

Test

Sym.

Parameter

Notes

Typ.

Max.

Unit

Conditions

Input Load Current

±0.5

µA

Max.

or GND

Output Leakage Current

±0.5

µA

Max.

OUT

or GND

CCS

Standby Current

1,3,6

µA

CMOS Level Inputs
V

Max.

CE#=RP#=V

±0.2V

0.2

TTL Level Inputs
V

Max.

CE#=RP#=V

CCAS

Auto Power-Save Current

1,5,6

µA

CMOS Level Inputs
V

Max.

CE#=GND±0.2V

CCD

Reset Power-Down Current

µA

RP#=GND±0.2V
I

OUT

(RY/BY#)=0mA

CCR

Read Current

1,6

CMOS Level Inputs
V

Max., CE#=GND

f=5MHz, I

OUT

=0mA

TTL Level Inputs
V

Max., CE#=GND

f=5MHz, I

OUT

=0mA

CCW

Word/Byte Write or Set Lock-

1,7

CCW

=2.7V-3.6V

Bit Current

CCW

=11.7V-12.3V

CCE

Block Erase, Full Chip Erase or

1,7

CCW

=2.7V-3.6V

Clear Block Lock-Bits Current

CCW

=11.7V-12.3V

CCWS

CCES

Word/Byte Write or

Block Erase Suspend Current

1,2

CE#=V

CCWS

CCW

Standby or Read Current

±2

±15

µA

CCW

CCWR

200

µA

CCW

CCWAS

CCW

Auto Power-Save Current

1,5,6

0.1

µA

CMOS Level Inputs
V

Max.

CE#=GND±0.2V

CCWD

CCW

Reset Power-Down Current

0.1

µA

RP#=GND±0.2V

CCWW

CCW

Word/Byte Write or Set Lock-

1,7

CCW

=2.7V-3.6V

Bit Current

CCW

=11.7V-12.3V

CCWE

CCW

Block Erase, Full Chip Erase

1,7

CCW

=2.7V-3.6V

or Clear Block Lock-Bits Current

CCW

=11.7V-12.3V

CCWWS

CCWES

CCW

Word/Byte Write or

Block Erase Suspend Current

200

µA

CCW

CCWH1/2

sharp

LHF80J05

Rev. 1.27

DC Characteristics (Continued)

=2.7V-3.6V

Sym.

Parameter

Notes

Min.

Max.

Unit

Test Conditions

Input Low Voltage

-0.5

0.8

Input High Voltage

2.0

+0.5

Output Low Voltage

3,7

0.4

Min.

=2.0mA

OH1

Output High Voltage
(TTL)

2.4

Min.

=-2.0mA

OH2

Output High Voltage
(CMOS)

0.85
V

Min.

=-2.5mA

-0.4

Min.

=-100µA

CCWLK

CCW

Lockout during Normal

Operations

4,7

1.0

CCWH1

CCW

during Block Erase, Full Chip

Erase, Word/Byte Write or Lock-Bit
Configuration Operations

2.7

3.6

CCWH2

CCW

during Block Erase, Full Chip

Erase, Word/Byte Write or Lock-Bit
Configuration Operations

11.7

12.3

LKO

Lockout Voltage

2.0

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V

voltage and T

=+25°C.

2. I

CCWS

and I

CCES

are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the

device's current draw is the sum of I

CCWS

or I

CCES

and I

CCR

or I

CCW

, respectively.

3. Includes RY/BY#.
4. Block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when V

CCW

CCWLK

, and not

guaranteed in the range between V

CCWLK

(max.) and V

CCWH1

(min.), between V

CCWH1

(max.) and V

CCWH2

(min.) and

above V

CCWH2

(max.).

5. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more

than 300ns while read mode.

6. About all of pin except describe Test Conditions, CMOS level inputs are either V

±0.2V or GND±0.2V, TTL level

inputs are either V

or V

7. Sampled, not 100% tested.
8. Applying 12V±0.3V to V

CCW

during erase/write can only be done for a maximum of 1000 cycles on each block. V

CCW

may be connected to 12V±0.3V for a total of 80 hours maximum.

sharp

LHF80J05

Rev. 1.27

6.2.4 AC Characteristics - Read-Only Operations

(1)

=2.7V-3.6V, T

=-40°C to +85°C

Sym.

Parameter

Notes

Min.

Max.

Unit

AVAV

Read Cycle Time

AVQV

Address to Output Delay

ELQV

CE# to Output Delay

PHQV

RP# High to Output Delay

600

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# High to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# High to Output in High Z

Output Hold from Address, CE# or OE# Change, Whichever
Occurs First

FVQV

BYTE# to Output Delay

FLQZ

BYTE# Low to Output in High Z

ELFV

CE# to BYTE# High or Low

3,4

NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t

ELQV

-t

GLQV

after the falling edge of CE# without impact on t

ELQV

3. Sampled, not 100% tested.
4. If BYTE# transfer during reading cycle, exist the regulations separately.

sharp

LHF80J05

Rev. 1.27

6.2.5 AC Characteristics - Write Operations

(1)

=2.7V-3.6V, T

=-40°C to +85°C

Sym.

Parameter

Notes

Min.

Max.

Unit

AVAV

Write Cycle Time

PHWL

RP# High Recovery to WE# Going Low

µs

ELWL

CE# Setup to WE# Going Low

WLWH

WE# Pulse Width

SHWH

WP#V

Setup to WE# Going High

100

VPWH

CCW

Setup to WE# Going High

100

AVWH

Address Setup to WE# Going High

DVWH

Data Setup to WE# Going High

WHDX

Data Hold from WE# High

WHAX

Address Hold from WE# High

WHEH

CE# Hold from WE# High

WHWL

WE# Pulse Width High

WHRL

WE# High to RY/BY# Going Low or SR.7 Going "0"

100

WHGL

Write Recovery before Read

QVVL

CCW

Hold from Valid SRD, RY/BY# High Z

2,4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High Z

2,4

FVWH

BYTE# Setup to WE# Going High

WHFV

BYTE# Hold from WE# High

NOTES:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are

the same as during read-only operations. Refer to AC Characteristics for read-only operations.

2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A

and D

for block erase, full chip erase, word/byte write or lock-bit configuration.

4. V

CCW

should be held at V

CCWH1/2

until determination of block erase, full chip erase, word/byte write or lock-bit

configuration success (SR.1/3/4/5=0).

5. If BYTE# switch during reading cycle, exist the regulations separately.

sharp

LHF80J05

Rev. 1.27

6.2.6 Alternative CE#-Controlled Writes

(1)

=2.7V-3.6V, T

=-40°C to +85°C

Sym.

Parameter

Notes

Min.

Max.

Unit

AVAV

Write Cycle Time

PHEL

RP# High Recovery to CE# Going Low

µs

WLEL

WE# Setup to CE# Going Low

ELEH

CE# Pulse Width

SHEH

WP#V

Setup to CE# Going High

100

VPEH

CCW

Setup to CE# Going High

100

AVEH

Address Setup to CE# Going High

DVEH

Data Setup to CE# Going High

EHDX

Data Hold from CE# High

EHAX

Address Hold from CE# High

EHWH

WE# Hold from CE# High

EHEL

CE# Pulse Width High

EHRL

CE# High to RY/BY# Going Low or SR.7 Going "0"

100

EHGL

Write Recovery before Read

QVVL

CCW

Hold from Valid SRD, RY/BY# High Z

2,4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High Z

2,4

FVEH

BYTE# Setup to CE# Going High

EHFV

BYTE# Hold from CE# High

NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive

WE# times should be measured relative to the CE# waveform.

2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A

and D

for block erase, full chip erase, word/byte write or lock-bit configuration.

4. V

CCW

should be held at V

CCWH1/2

until determination of block erase, full chip erase, word/byte write or lock-bit

configuration success (SR.1/3/4/5=0).

5. If BYTE# switch during reading cycle, exist the regulations separately.

sharp

RP#(P)

PLPH

PLRZ

High Z

("1")

("0")

PLPH

RY/BY#(R)

(SR.7)

RP#(P)

2VPH

(C)RP# rising Timing

2.7V

RP#(P)

(A)Reset During Read Array Mode

(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration

High Z

("1")

("0")

RY/BY#(R)

(SR.7)

LHF80J05

Rev. 1.27

6.2.7 Reset Operations

Figure 20. AC Waveform for Reset Operation

Reset AC Specifications

Sym.

Parameter

Notes

Min.

Max.

Unit

PLPH

RP# Pulse Low Time

100

PLRZ

RP# Low to Reset during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-Bit Configuration

1,2

µs

2VPH

2.7V to RP# High

2,3

100

NOTES:
1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,

the reset will complete within 100ns.

2. A reset time, t

PHQV

, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are

valid. Refer to AC Characteristics - Read-Only Operations for t

PHQV

3. When the device power-up, holding RP# low minimum 100ns is required after V

has been in predefined range and also

has been in stable there.

sharp

LHF80J05

Rev. 1.27

6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance

(3)

=2.7V-3.6V, T

=-40°C to +85°C

CCW

=2.7V-3.6V

CCW

=11.7V-12.3V

Sym.

Parameter

Notes

Min.

Typ.

(1)

Max.

Min.

Typ.

(1)

Max.

Unit

WHQV1

Word Write Time

32K word Block

200

µs

EHQV1

4K word Block

200

µs

Byte Write Time

64K byte Block

200

µs

8K byte Block

200

µs

Block Write Time

32K word Block

1.1

0.66

(In word mode)

4K word Block

0.15

0.5

0.12

Block Write Time

64K byte Block

2.2

1.4

(In byte mode)

8K byte Block

0.3

0.25

WHQV2

EHQV2

Block Erase Time

32K word Block
64K byte Block

1.2

0.9

4K word Block
8K byte Block

0.6

0.5

Full Chip Erase Time

22.8

114

17.5

WHQV3

EHQV3

Set Lock-Bit Time

200

µs

WHQV4

EHQV4

Clear Block Lock-Bits Time

0.69

WHRZ1

EHRZ1

Word/Byte Write Suspend Latency Time to
Read

µs

WHRZ2

EHRZ2

Block Erase Suspend Latency Time to
Read

µs

ERES

Latency Time from Block Erase Resume
Command to Block Erase Suspend
Command

600

µs

NOTES:
1. Typical values measured at T

=+25°C and V

=3.0V, V

CCW

=3.0V or 12.0V. Assumes corresponding lock-bits are not

set. Subject to change based on device characterization.

2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. A latency time is required from issuing suspend command(WE# or CE# going high) until RY/BY# going High Z or SR.7

going "1".

5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter

than t

ERES

and both commands are written repeatedly, a longer time is required than standard block erase until the

completion of the operation.

sharp

Rev. 1.10

A-1 RECOMMENDED OPERATING CONDITIONS

A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

Figure A-1. AC Timing at Device Power-Up

For the AC specifications t

, t

in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS"

described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.

2VPH

GND

(min)

RP#

(P)

PHQV

CCW

GND

CCWH1/2

(V)

CE#

(E)

WE#

(W)

OE#

(G)

WP#

(S)

(D/Q)

DATA

High Z

Valid

Output

ELQV

GLQV

(A)

ADDRESS

Valid

(RST#)

)

Address

AVQV

*1 t

5VPH

for the device in 5V operations.

*2 To prevent the unwanted writes, system designers should consider the V

CCW

) switch, which connects V

CCW

)

to GND during read operations and V

CCWH1/2

PPH1/2

) during write or erase operations.

PPH1/2

)

See the application note AP-007-SW-E for details.

sharp

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.

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EUROPE

JAPAN

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Phone: (1) 360-834-2500
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Fast Info: (1) 800-833-9437
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Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
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Electronic Components & Devices
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Phone: (81) 6-6621-1221
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(Taiwan) Corporation
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438A, Alexandra Road, #05-01/02
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HONG KONG

SHARP Microelectronics of China
(Shanghai) Co., Ltd.
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Phone: (86) 21-5854-7710/21-5834-6056
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SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
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Phone: (86) 755-3273731
Fax: (86) 755-3273735

Part Number LH28F800BJHE-PBTL90