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Part Number ACS8510

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Synchronous Equipment Timing Source
for SONET or SDH Network Elements
ACS8510 SETS
Description
Features
Block Diagram
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
ADVANCED COMMUNCIATIONS
FINAL
Revision 2.07/Jan 2001 г2001 Semtech Corp
www.semtech.com
Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifi-
cations
Accepts 14 individual input reference clocks
Generates 11 output clocks
Supports Free-Run, Locked and Holdover
modes of operation
Robust input clock source quality monitoring on
all inputs
Automatic hit-less source switchover on loss
of input
Phase build-out for output clock phase conti-
nuity during input switchover and mode transi-
tions
Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 v operation. 5 v I/O compatible
Operating temperature (ambient) -40°C to
+85°C
Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
DPLL/Freq. S ynthesis
T
OUT0
selector
T
OUT4
selector
Chip C lock
Generator
Div ider
PFD
DPLL/F req. Synthesis
Div ider
Monitors
Dig ital
Loop
Filter
A PLL
Frequency
Dividers
M icropro cessor
Port
14 Inp ut
Reference
Source
includin g:
AM I 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 M Hz
DTO
Dig ital
Loop
Filter
PFD
11 Outp ut Ports
includin g:
1.544/2.048 M Hz
3.088/4.096 M Hz
6.176/8.182 M Hz
12.352/16.384 M Hz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
AM I 64/8 kHz
2 kHz MFrSy nc
8 kHz FrSy nc
Input
Ports
6xT
IN1
4xT
IN2
4xT
IN3
Output
Ports
2xT
OUT 4
7xT
OUT 0
MFrSync
FrSync
TCXO (*OCXO)
CLK
IEEE
1149.1
JTAG
T CK
TDI
TMS
T RST
TDO
Priority
T able
Register
Set
Priority
T able
Register
Set
DTO
MFrSync
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Revision 2.07/Jan 2001 г2001 Semtech Corp
www.semtech.com
2
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
Table of Contents
Pin diagram................................................................................................................................................3
Pin descriptions.........................................................................................................................................4
Functional description...............................................................................................................................7
Electrical specification............................................................................................................................45
Microprocessor interface timing characteristics.......................................................................................56
Package information................................................................................................................................65
Application information............................................................................................................................67
Revision History.......................................................................................................................................68
Order information....................................................................................................................................69
Local oscillator clock..........................................................................................................................................................8
Input Interfaces..................................................................................................................................................................8
Over voltage protection.......................................................................................................................................................8
Input reference clock ports................................................................................................................................................9
Input wander and jitter tolerance...................................................................................................................................11
Output clock ports...........................................................................................................................................................13
Output wander and jitter..................................................................................................................................................14
Phase variation.................................................................................................................................................................16
Phase build-out.................................................................................................................................................................17
Microprocessor interface................................................................................................................................................17
Interrupt enable and clear...............................................................................................................................................19
Register map description.................................................................................................................................................21
Register map description.................................................................................................................................................25
Selection of input reference clock source.....................................................................................................................33
Clock quality monitoring..................................................................................................................................................34
Activity monitoring...........................................................................................................................................................35
Modes of operation..........................................................................................................................................................38
Protection facility.............................................................................................................................................................39
JTAG..............................................................................................................................................................................42
Power on reset - PORB.....................................................................................................................................................42
Absolute maximum range...............................................................................................................................................45
Operating conditions.......................................................................................................................................................45
TTL DC characterisitics...................................................................................................................................................45
PECL DC characteristics..................................................................................................................................................47
LVDS DC characteristics..................................................................................................................................................48
AMI DC characteristics....................................................................................................................................................49
Jitter characteristics........................................................................................................................................................52
JTAG timing........................................................................................................................................................................55
Motorola mode..................................................................................................................................................................56
Intel mode................................................................................................................................................................58
Multiplexed mode.............................................................................................................................................................60
Serial mode.......................................................................................................................................................................62
EEPROM mode.................................................................................................................................................................64
Simplified application schematic...................................................................................................................................67
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Revision 2.07/Jan 2001 г2001 Semtech Corp
www.semtech.com
3
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
Figure 1: Top view of 100 pin LQFP package.
NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.
100 SONSDHB
99
MSTSLVB
9
8
IC
9
7
IC
9
6
IC
95
TO9
94
TO5
93
TO4
92
DGND
91
VDD
90
TO3
89TO2
88
TO1
87
DGND
86
VDD
85
VDD
84
DGND
83
AD0
82
AD1
81
AD2
80
AD3
79AD4
78
AD5
77
AD6
76
AD7
75
RDY
74
PORB
73
ALE
72
RDB
71
WRB
70
CSB
69A0
68
A1
67
A2
66
A3
65
A4
64
A5
63
A6
62
DGND
61
VDD
60
UPSEL0
59UPSEL1
58
UPSEL2
57
I14
56
I13
55
I12
54
I11
53
I10
52
I9
51
I8
ACS8510
SDH/SONET SETS
Rev 2.x
1
1
AGND
2
TRST
3
IC
4
NC
5
AGND
6
VA1+
7
TMS
8
INTREQ
9TCK
10
REFCLK
11
DGND
12
VD+
13
VD+
14
DGND
15
DGND
16
VD+
17
NC
18
SRCSW
19VA2+
20
AGND
21
TDO
22
IC
23
TDI
24
I1
25
I2
26
VAMI+
27
TO8NEG
28
TO8POS
29GND_AMI
30
FrSync
31
MFrSync
32
GND_DIFF
33
VDD_DIFF
34
TO6POS
35
TO6NEG
36
TO7POS
37
TO7NEG
38
GND_DIFF
39VDD_DIFF
40
I5POS
41
I5NEG
42
I6POS
43
I6NEG
44
VDD5
45
SYNC2K
46
I3
47
I4
48
I7
49DGND
50
VDD
Pin Diagram
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Revision 2.07/Jan 2001 г2001 Semtech Corp
www.semtech.com
4
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
N
I
P
L
O
B
M
Y
S
O
I
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
/
E
M
A
N
7
1
,
4
C
N
-
-
d
e
t
c
e
n
n
o
C
t
o
N
t
a
o
l
F
o
t
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v
a
e
L
:
,
6
9
,
2
2
,
3
8
9
,
7
9
C
I
-
-
d
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t
c
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n
n
o
C
y
ll
a
n
r
e
t
n
I
t
a
o
l
F
o
t
e
v
a
e
L
:
Pin Descriptions
Power
No connections
Note: I = input, O = output, P = power, TTL
U
= TTL input with pull-up resistor, TTL
D
= TTL input with pull-down resistor
N
I
P
L
O
B
M
Y
S
O
I
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
/
E
M
A
N
6
1
,
3
1
,
2
1
+
D
V
P
-
:
e
g
a
tl
o
v
y
l
p
p
u
S
3
.
3
+
,
n
o
it
c
e
s
g
o
l
a
n
a
n
i
s
e
t
a
g
o
t
y
l
p
p
u
s
l
a
ti
g
i
D
%
0
1
-
/
+
.
s
tl
o
V
6
2
+
I
M
A
V
P
-
:
e
g
a
tl
o
v
y
l
p
p
u
S
%
0
1
-
/
+
.
s
tl
o
V
3
.
3
+
,t
u
p
t
u
o
I
M
A
o
t
y
l
p
p
u
s
l
a
ti
g
i
D
9
3
,
3
3
F
F
I
D
_
D
D
V
P
-
:
e
g
a
tl
o
v
y
l
p
p
u
S
.
s
tl
o
V
3
.
3
+
,
s
t
r
o
p
l
a
it
n
e
r
e
ff
i
d
r
o
f
y
l
p
p
u
s
l
a
ti
g
i
D
%
0
1
-
/
+
4
4
5
D
D
V
P
-
5
D
D
V
t
c
e
n
n
o
C
.
s
n
i
p
t
u
p
n
i
o
t
e
c
n
a
r
e
l
o
t
s
tl
o
V
5
+
r
o
f
y
l
p
p
u
s
l
a
ti
g
i
D
:
r
o
f
D
D
V
o
t
t
c
e
n
n
o
C
.v
5
+
o
t
g
n
i
p
m
a
l
c
r
o
f
)
%
0
1
-
/
+
(
s
tl
o
v
5
+
o
t
s
n
i
p
t
u
p
n
i
,
g
n
i
p
m
a
l
c
o
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f
g
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it
a
o
lf
e
v
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e
L
.v
3
.
3
+
o
t
g
n
i
p
m
a
l
c
.v
5
.
5
+
o
t
p
u
t
n
a
r
e
l
o
t
,
5
8
,
1
6
,
0
5
1
9
,
6
8
D
D
V
P
-
:
e
g
a
tl
o
v
y
l
p
p
u
S
%
0
1
-
/
+
.
s
tl
o
V
3
.
3
+
,
c
i
g
o
l
o
t
y
l
p
p
u
s
l
a
ti
g
i
D
6
+
1
A
V
P
-
:
e
g
a
tl
o
v
y
l
p
p
u
S
.
s
tl
o
V
3
.
3
+
,
L
L
P
g
n
i
y
p
it
l
u
m
k
c
o
l
c
o
t
y
l
p
p
u
s
g
o
l
a
n
A
%
0
1
-
/
+
9
1
+
2
A
V
P
-
e
g
a
tl
o
v
y
l
p
p
u
S
%
0
1
-
/
+
.
s
tl
o
V
3
.
3
+
,
L
L
P
t
u
p
t
u
o
o
t
y
l
p
p
u
s
g
o
l
a
n
A
:
,
5
1
,
4
1
,
1
1
,
4
8
,
2
6
,
9
4
2
9
,
7
8
D
N
G
D
P
-
d
n
u
o
r
G
y
l
p
p
u
S
c
i
g
o
l
r
o
f
d
n
u
o
r
g
l
a
ti
g
i
D
:
9
2
I
M
A
_
D
N
G
P
-
d
n
u
o
r
G
y
l
p
p
u
S
t
u
p
t
u
o
I
M
A
r
o
f
d
n
u
o
r
g
l
a
ti
g
i
D
:
8
3
,
2
3
F
F
I
D
_
D
N
G
P
-
d
n
u
o
r
G
y
l
p
p
u
S
s
t
r
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l
a
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n
e
r
e
ff
i
d
r
o
f
d
n
u
o
r
g
l
a
ti
g
i
D
:
0
2
,
5
,
1
D
N
G
A
P
-
d
n
u
o
r
G
y
l
p
p
u
S
d
n
u
o
r
g
g
o
l
a
n
A
:
background image
Revision 2.07/Jan 2001 г2001 Semtech Corp
www.semtech.com
5
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
Others
N
I
P
L
O
B
M
Y
S
O
I
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
/
E
M
A
N
2
T
S
R
T
I
L
T
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D
t
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R
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o
C
G
A
T
J
y
r
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d
n
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o
B
G
A
T
J
e
l
b
a
n
e
o
t
1
=
T
S
R
T
:
c
i
g
o
l
G
A
T
J
(
n
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it
a
r
e
p
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l
a
m
r
o
n
r
o
f
0
=
T
S
R
T
.
e
d
o
m
n
a
c
S
.
g
n
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a
o
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