Overview
The LC895994 is a CD-R LSI that provides a wide range
of functions including CD-ROM decoding (including
ECC) and encoding, subcode Q encoding (CRC addition)
and decoding, CD encoding, ATIP decoding and CLV
servo, and an IDE interface that includes the register
block.
Features
· ECC and EDC correction/addition for the CD-ROM
data (during decoding and encoding)
· ATIP decoding and CRC checking for both encoding
and decoding
· CLV servo control using ATIP data during encoding
· CIRC code insertion and EFM modulation during
encoding
· Support for PCA random EFM output during encoding
· Support for CD-ReWritable (CD-RW) Write Strategy
signal output
· Access to buffer RAM from microcontroller via
LC895994
· Built-in ATAPI (IDE) interface
· Speeds of 12
×
for decoding and 4
×
for encoding
-- Frequencies
Decoding: 17.2872 MHz
Encoding: 17.2872 MHz without Write Strategy
support
69.1488 MHz with Write Strategy
support
· IDE Transfer rate: 13.3 MB/s when using 16-bit data
path 80-ns DRAM chips
· Buffer RAM sizes between 1 and 32 megabits (using 16-
bit DRAMs)
· User control over sizes of CD main channel, C2 flag
areas in buffer RAM
· Built-in batch transfer function for transferring entire
CD main channel, C2 flag, or subcode area in a single
operation
· Built-in multiblock transfer function for transferring
multiple blocks in a single operation
Package Dimensions
unit: mm
3153A-QFP160E
CMOS IC
42098RM (OT) No. 5824-1/7
Preliminary
SANYO: QIP160E
[LC895994]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
CD-R Encoder/Decoder LSI with
Built-in ATAPI (IDE) Interface
LC895994
Ordering number : EN
*
5824
No. 5824-2/7
LC895994
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
0.3 to +7.0
V
I/O voltage
V
I
, V
O
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
Ta
70°C
600
mW
Operating temperature
Topr
30 to +70
°C
Storage temperature
Tstg
55 to +125
°C
Solder resistance (Pins only)
10 seconds
260
°C
Specifications
Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
V
IH
TTL levels, for pin types 1 and 7
2.2
V
Input low-level voltage
V
IL
0.8
V
Input high-level voltage
V
IH
TTL levels, for pin types 8 and 9, with pull-up
2.2
V
resistors
Input low-level voltage
V
IL
0.8
V
Input high-level voltage
V
IH
TTL levels, for pin types 2 and 10, with
2.5
V
Schmitt inputs
Input low-level voltage
V
IL
0.6
V
Output high-level voltage
V
OH
I
OH
= 2 mA, for pin type 6
V
DD
-- 2.1
V
Output low-level voltage
V
OL
I
OL
= 2 mA, for pin type 6
0.4
V
Output high-level voltage
V
OH
I
OH
= 24 mA, for pin type 3
V
DD
-- 2.1
V
Output low-level voltage
V
OL
I
OL
= 24 mA, for pin type 3
0.4
V
Output high-level voltage
V
OH
I
OH
= 2 mA, for pin types 4, 7, and 8
V
DD
-- 2.1
V
Output low-level voltage
V
OL
I
OL
= 2 mA, for pin types 4, 7, and 8
0.4
V
Output high-level voltage
V
OH
I
OH
= 24 mA, for pin types 5 and 10
V
DD
-- 2.1
V
Output low-level voltage
V
OL
I
OL
= 24 mA, for pin types 5 and 10
0.4
V
Output low-level voltage
V
OL
I
OL
= 2 mA, for pin type 9.
0.4
V
Input leakage current
I
IL
V
I
= V
SS
, V
DD
, for pin types 1, 2, 7, and 10
10
+10
µA
Output leakage current
When set to high-impedance output:
10
+10
µA
For pin types 4, 5, 7, and 10.
Pull-up resistance
R
UP
For pin types 8 and 9
40
80
160
k
DC Characteristics
at Ta = 30 to +70°C, V
SS
= 0 V, V
DD
= 4.5 to 5.5 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
4.5
5.0
5.5
V
Input voltage range
V
IN
0
V
DD
V
Allowable Operating Range
at Ta = 30 to +70°C, V
SS
= 0 V
The pin types above refer to the following groups.
Input
(1) SUA0 to SUA7, TEST0 to TEST6, RESET
(2) BCK, BICLKIN, BIDATAI, C2PO, DA0 to DA2, LOCKIN, LRCK, PLLOUTIN, ROUGH, SBSO, SCOR, SDATA,
WFCK, CS, CS1FX, CS3FX, DIOR, DIOW, DMACK, HRST, RD, WR
Output
(3) EFM
(4) CLVMDP, CLVMDS, FSW
(5) DMARQ, HINTRQ, IORDY, IOCS16
(6) DATACKO, EFMG, EFMGATE0 to EFMGATE3, EXCK, LOCK, MCK, MON, PSUBSYNC, RA0 to RA9,
SUBSYNC, CAS0, CAS1, ERROR, EXTACK, FRCK, LWE, OE, RAS0, RAS1, UWE
Input
(7) ATIPSYNC, Reserve0 to Reserve5
(8) D0 to D7, IO0 to IO15
(9) INT0 to INT1, SWAIT
(10) DD0 to DD15, DASP, PDIAG
Block Diagram
No. 5824-3/7
LC895994
*2 BCK, SDATA, LRCK, C2PO
*3 DD0 to DD15, DASP, PDIAG
*4 CS1FX, CS3FX, DA0 to DA2, DIOR, DIOW, DMACK
*5 DMARQ, HINTRQ, IOCS16, IORDY
*6 RD, WR, SUA0 to SUA6, CS
*7 D0 to D7
*8 IO0 to IO15
*9 RA0 to RA9, RAS0, RAS1, CAS0, CAS1, OE, UWE, LWE
*10 PLLOUTIN, ROUGH, LOCKIN, BICLKIN, BIDATAIN
*11 ERROR, LOCK, CLV
+
(MDP), CLV
(MDS), MON, FSW
*12 SUBSYNC, PSUBSYNC, FRCK, EFM, EFMG, EFMGATE3 to EFMGATE0, EXTACK, DATACKO
**1 HISIDE (WD25C32) is made by WESTERN DIGITAL.
Pin Descriptions
No. 5824-4/7
LC895994
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin No.
Pin Name
Type
Description
1
V
SS
P
2
Reserve0
O
Reserved for future expansion (Must be left open if unused.)
3
Reserve1
I
Reserved for future expansion (Must be tied to ground if unused.)
4
Reserve2
I
Reserved for future expansion (Must be tied to ground if unused.)
5
TEST1
I
Test pin (connect to V
SS
)
6
XTALCK
I
Crystal oscillator circuit input pin (17.2872 to 69.1488 MHz)
7
XTAL
O
Crystal oscillator circuit output pin
8
TEST2
I
Test pin (connect to V
SS
)
9
MCK
O
Master Clock output pin
10
TEST3
I
Test pin (connect to V
SS
)
11
PSUBSYNC
O
Pseudo-subcode synchronization output
12
EXTACK
O
ATIP synchronization acknowledge signal output
13
TEST4
I
Test pin (connect to V
SS
)
14
V
DD
P
15
V
SS
P
16
CLV
+
(MDP)
O
17
CLV
(MDS)
O
CLV servo signal output pins
18
MON
O
19
FSW
O
20
V
DD
P
21
V
SS
P
22
PLLOUTIN
I
Wobble signal carrier clock input pin
23
ROUGH
I
Rough CLV servo wobble signal input pin
24
LOCKIN
I
CD decoder lock signal input pin
25
LOCK
O
CLV servo lock monitor pin
26
ERROR
O
ATIP parity error detection pin
27
ATIPSYNC
B
ATIP synchronization signal I/O pin
28
BIDATAI
I
Biphase data input pin
29
BICLKIN
I
Biphase data transfer clock input pin
30
DATACKO
O
4.3218 MHz (normal speed) oscillator output
31
IO0
B
32
IO1
B
33
IO2
B
34
IO3
B
35
IO4
B
Data signal pins for ROM encoder/decoder buffer RAM, with pull-up resistors
36
IO5
B
37
IO6
B
38
IO7
B
39
IO8
B
40
V
DD
P
41
V
SS
P
Continued on next page.
No. 5824-5/7
LC895994
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin No.
Pin Name
Type
Description
42
IO9
B
43
IO10
B
44
IO11
B
45
IO12
B
Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
46
IO13
B
47
IO14
B
48
IO15
B
49
V
SS
P
50
RA0
O
51
RA1
O
52
RA2
O
53
RA3
O
54
RA4
O
Address signal pins for ROM encoder/decoder DRAM
55
RA5
O
56
RA6
O
57
RA7
O
58
RA8
O
59
RA9
O
60
V
DD
P
61
V
SS
P
62
RAS0
O
DRAM RAS signal output pins
63
RAS1
O
64
CAS0
O
DRAM CAS signal output pins
65
CAS1
O
66
OE
O
DRAM output enable signal output pin
67
UWE
O
DRAM upper write enable signal output pin
68
LWE
O
DRAM lower write enable signal output pin
69
TEST0
I
Test pin (connect to V
SS
)
70
V
DD
P
71
EXCK
O
Subcode data read shift clock output pin
72
WFCK
I
Subcode frame synchronization input pin
73
SBSO
I
Subcode serial data input pin
74
SCOR
I
Subcode block synchronization input pin
75
V
SS
P
76
BCK
I
Serial data input clock input pin
77
SDATA
I
Serial data input pin
78
LRCK
I
44.1-kHz strobe signal input pin
79
C2PO
I
C2 pointer input pin
80
V
DD
P
81
V
SS
P
82
HRST
I
83
DASP
B
IDE pins
84
CS3FX
I
85
CS1FX
I
86
V
DD
P
87
DA2
I
88
DA0
I
IDE pins
89
PDIAG
B
Continued on next page.
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