PM5315

Preliminary

PMC-Sierra,Inc.

SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s

SPECTRA-2488

PMC-2000326 (p1)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

FEATURES

· Monolithic SONET/SDH Payload

Extractor/Aligner for use in interface
applications, operating at serial
interface speeds of up to 2488 Mbit/s:

single STS-48c (STM-16/AU4-16c);

single STS-48 (STM-16/AU4-
4c/AU4/AU3/TU3);

quad STS-12c (STM-4/AU4-4c);

quad STS-12 (STM-
4/AU4/AU3/TU3).

· In single STS-48/STM-16 mode,

supports a duplex 16-bit 155.52 MHz
differential PECL line side interface for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.

· In quad STS-12/STM-4 mode,

supports four duplex 8-bit 77.76 MHz
TTL compatible line side interfaces for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.

· Provides termination for SONET

Section, Line and Path overhead or
SDH Regenerator Section, Multiplexer
Section and High Order Path
overhead.

· In single STS-48/STM-16 mode

provides a 32-bit 77.76 MHz ADD and
DROP TelecomBus.

· In quad STS-12/STM-4 mode provides

four 8-bit 77.76 MHz ADD and DROP
TelecomBus Interfaces.

· Maps SONET/SDH payloads to

system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.

· The entire SONET/SDH transport and

path overheads are extracted to and
inserted from dedicated pins.

· Frames to the SONET/SDH receive

stream and inserts framing bytes and
STS identification into the transmit
stream and processes or inserts the
transport overhead.

· Interprets or generates the STS (AU)

pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.

· Provides Time Slot Interchange (TSI)

function at the ADD and DROP
TelecomBus Interfaces for grooming
any legal mix of SONET/SDH paths.

· Supports Automatic Protection

Switching (APS):

Ring control port communication of
path REI and path RDI alarms;

Filters the APS channel (K1,K2)
bytes into internal registers; inserts
the APS channel into the transmit
stream.

· Supports line loopback from the line

side receive stream to the transmit
stream and diagnostic loopback from
an ADD TelecomBus interface to a
DROP TelecomBus interface.

· Provides a standard five signal IEEE

1149.1 JTAG test port for boundary
scan board test purposes.

Rx Ring

Control

Port

OC-48 Mode:
16-bit x 155.52
Mbit/s PECL

4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL

OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus

4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus

OC-48 Mode:
16-bit x 155.52
Mbit/s PECL

4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL

OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus

4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus

Status

Information

(STS-12) Transmit Path Processing Slice

Tx Pointer
Interpreter

(STS/AU-

TU3)

T x

Telecom

Aligner

Add Bus

P R B S

Generator/

Monitor

Path

Trace

Processor

Tx Path O/H

Processor

T x

TelecomBus

System

Interface

Tx Timeslot
Interchange

Transmit Path

O / H

16-bit

Microprocessor

Bus

Microprocessor Interface

Quad 622

or 2488

M o d e

Test Data

JTAG Test

Access Port

Tx Line

Interface

Transmit

Transport

O / H

Transmit O/H
Clock, Frame

Pulse

Transmit

Section/Line

DCC Clock

Section

Trace

Processor

Tx Transport

O/H Processor

Control

and

Status

Information

(STS-12) Receive Path Processing Slice

Path

Trace

Processor

Rx Path O/H

Processor

Rx Timeslot
Interchange

TelecomBus

System

Interface

Receive Path

O v e r h e a d

Bit-interleaved

Parity Error

Rx Line

Interface

Telecom

Aligner

Drop Bus

P R B S

Generator/

Monitor

Receive O/H Clock,

Frame Pulse

Receive Transport

O v e r h e a d

Receive Section/Line

DCC and Clock

A l a r m
Reporting

S O N E T / S D H

Alarm

Reporting
Controller

Rx APS

Sync

Extractor

Bit Error

Monitor

Section

Trace

Processor

RX Transport

O/H Processor

Tx Ring

Control Port

BLOCK DIAGRAM

Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200

SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s

To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator

All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com

PMC-2000326 (p1)
© Copyright PMC-Sierra,
Inc. 2000. All rights reserved.
March 2000

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

Preliminary

PM5315 SPECTRA-2488

· Provides a generic 16-bit

microprocessor bus interface for
configuration, control, and status
monitoring.

· Low power 1.8 V CMOS core logic with

3.3 V CMOS/TTL compatible digital
inputs and digital outputs. PECL inputs
and outputs are 3.3 V compatible.

· Industrial temperature range (-40°C to

+85°C).

· 520 pin Super BGA package.

APPLICATIONS

· Channelized STS-48/STM-16 or

4 x STS-12/STM-4 Interfaces for:

Optical Cross Connects;

Digital Cross Connects;

Router and Switch Line Cards;

ADM Aggregate Cards for TDM and
Multiservice applications;

Terminal Multiplexers.

TYPICAL APPLICATIONS

STS-48/STM-16 APPLICATION WITH VT/TU POINTER PROCESSING/ALIGNMENT

PM5315

SPECTRA-

2488

Drop

ACK

AD[31:0], ADP[4:1]

APL[4:1]

AJ0J1[4:1]

Add

PM5363

TUPP+622

DPL[1]

DD1[7:0], DDP[1]

DJ0J1[1]

D C K

DPL[4]

DD4[7:0], DDP[4]

DJ0J1[4]

D C K

PM5363

TUPP+622

DPL[3]

DD3[7:0], DDP[3]

DJ0J1[3]

D C K

PM5363

TUPP+622

DPL[2]

DD2[7:0], DDP[2]

DJ0J1[2]

D C K

16-bit x

155.52
Mbit/s

To VT/TU Cross-

Connect or

Tributary Cards

2488 Mbit/s

Optical

Interface

Clock

Synthesis

Clock/Data

Recovery

Serial/

Parallel

Converter

Optical

Transceiver

PM5363

TUPP+622

PM5315

SPECTRA-2488

ACK

AD[31:0], ADP[4:1]

APL[4:1]

AJ0J1[4:1]

DD[31:0], DDP[4:1]

DJ0J1[4:1]

DCK

DPL[4:1]

DFP

PM7390

S/UNI-MACH48

POS-PHY

Level 3/
UTOPIA

Level 3

To a

Datalink-

Layer

Device

16-bit x

155.52
Mbit/s

2488 Mbit/s

Optical

Interface

Clock

Synthesis

Clock/Data

Recovery

Serial/

Parallel

Converter

Optical

Transceiver

STS-48/STM-16 APPLICATION WITH POS/ATM PROCESSING

Part Number PM5315

Document Outline