Document Outline

• Contents
• Figures
• Tables
• Registers
• Timing Diagrams
• Preface
• Revision History
• 1 Introduction
  • 1.1 Features
  • 1.2 Company and Product Background
    • 1.2.1 PCI 9054 I/O Accelerator
    • 1.2.2 Data Pipe Architecture Technology
      • 1.2.2.1 Dual DMA Channels
      • 1.2.2.2 PCI Initiator (Direct Master)
      • 1.2.2.3 PCI Target (Direct Slave)
      • 1.2.2.4 PCI Messaging
    • 1.2.3 PCI 9054 PCI Applications
      • 1.2.3.1 High Performance Motorola MPC850 or MPC860 PowerQUICC Designs
      • 1.2.3.2 High Performance CompactPCI Adapter Designs
        • 1.2.3.2.1 Hot Swap Capable
        • 1.2.3.2.2 Hot Swap Friendly
      • 1.2.3.3 PCI Bus Embedded Host Design
    • 1.2.4 PCI 9054 Major Features
    • 1.2.5 PCI 9054 Data Assignment Convention
      • 1.2.5.1 PCI 9050/9080 Compatibility
      • 1.2.5.2 Pin Compatibility
      • 1.2.5.3 Register Compatibility
    • 1.2.6 PCI 9054, PCI 9080, and PCI 9050 Comparison
    • 1.2.7 PCI 9054 Signal Listing (M, C, or J Modes)
• 2 M Mode Bus Operation
  • 2.1 PCI Bus Cycles
    • 2.1.1 PCI Target Command Codes
    • 2.1.2 PCI Master Command Codes
      • 2.1.2.1 DMA Master Command Codes
      • 2.1.2.2 Direct Local-to-PCI Command Codes
    • 2.1.3 PCI Arbitration
  • 2.2 Local Bus Cycles
    • 2.2.1 Local Bus Arbitration
    • 2.2.2 PCI Initiator
    • 2.2.3 PCI Target
    • 2.2.4 Wait State Control
      • 2.2.4.1 Wait States„Local Bus
      • 2.2.4.2 Wait States„PCI Bus
    • 2.2.5 Burst Mode and Continuous Burst Mode (Bterm ¨Burst Terminateˇ Mode)
      • 2.2.5.1 Burst and Bterm Modes
      • 2.2.5.2 Burst-4 Lword Mode
        • 2.2.5.2.1 Continuous Burst Mode (Bterm ¨Burst Terminateˇ Mode)
      • 2.2.5.3 Partial Lword Accesses
    • 2.2.6 Local Bus Read Accesses
    • 2.2.7 Local Bus Write Accesses
    • 2.2.8 PCI Target Accesses to 8- or 16Bit Local Bus
    • 2.2.9 Local Bus Data Parity
  • 2.3 Big Endian/Little Endian
    • 2.3.1 PCI Bus Little Endian Mode
    • 2.3.2 Local Bus Big/Little Endian Mode
      • 2.3.2.1 32-Bit Local Bus„Big Endian Mode
      • 2.3.2.2 16-Bit Local Bus„Big Endian Mode
      • 2.3.2.3 8-Bit Local Bus„Big Endian Mode
      • 2.3.2.4 Local Bus Big/Little Endian Mode Accesses
  • 2.4 Serial EEPROM
    • 2.4.1 Vendor and Device ID Registers
      • 2.4.1.1 Serial EEPROM Initialization
      • 2.4.1.2 Local Initialization
    • 2.4.2 Serial EEPROM Operation
      • 2.4.2.1 Long Serial EEPROM Load
      • 2.4.2.2 Extra Long Serial EEPROM Load
      • 2.4.2.3 New Capabilities Function Support
      • 2.4.2.4 Recommended Serial EEPROMs
      • 2.4.2.5 Serial EEPROM Initialization
    • 2.4.3 Internal Register Access
      • 2.4.3.1 PCI Bus Access to Internal Registers
      • 2.4.3.2 Local Bus Access to InternalRegisters
    • 2.4.4 Serial EEPROM Timing Diagrams
• 3 M Mode Functional Description
  • 3.1 Reset Operation
    • 3.1.1 PCI Bus Input RST#
    • 3.1.2 Software Reset
  • 3.2 PCI 9054 Initialization
  • 3.3 Response to FIFO Full orEmpty
  • 3.4 Direct Data Transfer Modes
    • 3.4.1 PCI Initiator Operation (Local Master-to-PCI Target)
      • 3.4.1.1 PCI Initiator Memory and I/O Decode
      • 3.4.1.2 PCI Initiator FIFOs
      • 3.4.1.3 PCI Initiator Memory Access
      • 3.4.1.4 PCI Initiator I/O Configuration Access
      • 3.4.1.5 PCI Initiator I/O
      • 3.4.1.6 RETRY# Capability
        • 3.4.1.6.1 PCI Initiator Write FIFO Full
        • 3.4.1.6.2 PCI Initiator Delayed Read
      • 3.4.1.7 PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles)
        • 3.4.1.7.1 PCI Initiator Configuration Cycle Example
      • 3.4.1.8 PCI Initiator PCI Dual Address Cycle
      • 3.4.1.9 PCI Initiator/Target Abort
      • 3.4.1.10 PCI Initiator Memory Write and Invalidate
    • 3.4.2 IDMA/SDMA Operation
      • 3.4.2.1 IDMA Operation
      • 3.4.2.2 SDMA Operation
    • 3.4.3 PCI Target Operation (PCI Masterto-Local Bus Access)
      • 3.4.3.1 PCI Target Lock
      • 3.4.3.2 PCI Target PCI v2.1 Delayed Read Mode
      • 3.4.3.3 PCI Target PCI Read Ahead Mode
      • 3.4.3.4 PCI Target Transfer
      • 3.4.3.5 PCI Target PCI-to-Local Address Mapping
        • 3.4.3.5.1 PCI Target Local Bus Initialization
        • 3.4.3.5.2 PCI Target PCI Initialization
        • 3.4.3.5.3 PCI Target Transfer Size
          • 3.4.3.5.3.1 PCI Target Example
      • 3.4.3.6 PCI Target Priority
    • 3.4.4 Deadlock Conditions
      • 3.4.4.1 Backoff
        • 3.4.4.1.1 Software/Hardware Solution for Systems without Backoff Capability
        • 3.4.4.1.2 Preempt Solution
      • 3.4.4.2 Software Solutions to Deadlock
  • 3.5 DMA Operation
    • 3.5.1 DMA PCI Dual Address Cycle
    • 3.5.2 Block DMA Mode
      • 3.5.2.1 Block DMA PCI DualAddressCycle
    • 3.5.3 Scatter/Gather DMA Mode
      • 3.5.3.1 Scatter/Gather DMA PCI DualAddress Cycle
      • 3.5.3.2 DMA Clear Count Mode
    • 3.5.4 DMA Memory Write and Invalidate
      • 3.5.4.1 DMA Abort
    • 3.5.5 DMA Priority
    • 3.5.6 DMA Channel 0/1 Interrupts
    • 3.5.7 DMA Data Transfers
      • 3.5.7.1 Local-to-PCI Bus DMA Transfer
      • 3.5.7.2 PCI-to-Local Bus DMA Transfer
      • 3.5.7.3 DMA Local Bus Error Condition
      • 3.5.7.4 DMA Unaligned Transfers
    • 3.5.8 Demand Mode DMA, Channel 0
    • 3.5.9 End of Transfer (EOT#) Input
    • 3.5.10 DMA Arbitration
    • 3.5.11 Local Bus Latency and PauseTimers
  • 3.6 M Mode Timing Diagrams
    • 3.6.1 M Mode PCI Initiator
    • 3.6.2 M Mode PCI Target
    • 3.6.3 M Mode DMA
• 4 C and J Modes Bus Operation
  • 4.1 PCI Bus Cycles
    • 4.1.1 PCI Target Command Codes
    • 4.1.2 PCI Master Command Codes
      • 4.1.2.1 DMA Master Command Codes
      • 4.1.2.2 Direct Local-to-PCI Command Codes
    • 4.1.3 PCI Arbitration
  • 4.2 Local Bus Cycles
    • 4.2.1 Local Bus Arbitration
    • 4.2.2 PCI Initiator
    • 4.2.3 PCI Target
    • 4.2.4 Wait State Control
      • 4.2.4.1 Wait States„Local Bus
      • 4.2.4.2 Wait States„PCI Bus
    • 4.2.5 Burst Mode and Continuous Burst Mode (Bterm ¨Burst Terminateˇ Mode)
      • 4.2.5.1 Burst and Bterm Modes
      • 4.2.5.2 Burst-4 Lword Mode
        • 4.2.5.2.1 Continuous Burst Mode (Bterm ¨Burst Terminateˇ Mode)
      • 4.2.5.3 Partial Lword Accesses
    • 4.2.6 Recovery States (J Mode Only)
    • 4.2.7 Local Bus Read Accesses
    • 4.2.8 Local Bus Write Accesses
    • 4.2.9 PCI Target Accesses to 8- or 16Bit Local Bus
    • 4.2.10 Local Bus Data Parity
  • 4.3 Big Endian/Little Endian
    • 4.3.1 PCI Bus Little Endian Mode
    • 4.3.2 Local Bus Big/Little Endian Mode
      • 4.3.2.1 32-Bit Local Bus„Big Endian Mode
      • 4.3.2.2 16-Bit Local Bus„Big Endian Mode
      • 4.3.2.3 8-Bit Local Bus„Big Endian Mode
      • 4.3.2.4 Local Bus Big/Little Endian Mode Accesses
  • 4.4 Serial EEPROM
    • 4.4.1 Vendor and Device ID Registers
      • 4.4.1.1 Serial EEPROM Initialization
      • 4.4.1.2 Local Initialization
    • 4.4.2 Serial EEPROM Operation
      • 4.4.2.1 Long Serial EEPROM Load
      • 4.4.2.2 Extra Long Serial EEPROM Load
      • 4.4.2.3 New Capabilities FunctionSupport
      • 4.4.2.4 Recommended Serial EEPROMs
      • 4.4.2.5 Serial EEPROM Initialization
    • 4.4.3 Internal Register Access
      • 4.4.3.1 PCI Bus Access to InternalRegisters
      • 4.4.3.2 Local Bus Access to InternalRegisters
    • 4.4.4 Serial EEPROM Timing Diagrams
• 5 C and J Modes Functional Description
  • 5.1 Reset Operation
    • 5.1.1 PCI Bus Input RST#
    • 5.1.2 Software Reset
  • 5.2 PCI 9054 Initialization
  • 5.3 Response to FIFO Full or Empty
  • 5.4 Direct Data Transfer Modes
    • 5.4.1 PCI Initiator Operation (Local Master-to-PCI Target)
      • 5.4.1.1 PCI Initiator Memory and I/O Decode
      • 5.4.1.2 PCI Initiator FIFOs
      • 5.4.1.3 PCI Initiator Memory Access
      • 5.4.1.4 PCI Initiator I/O Configuration Access
      • 5.4.1.5 PCI Initiator I/O
      • 5.4.1.6 PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles)
        • 5.4.1.6.1 PCI Initiator Configuration Cycle Example
      • 5.4.1.7 PCI Initiator PCI Dual Address Cycle
      • 5.4.1.8 PCI Initiator/Target Abort
      • 5.4.1.9 PCI Initiator Memory Write and Invalidate
    • 5.4.2 PCI Target Operation (PCI Masterto-Local Bus Access)
      • 5.4.2.1 PCI Target Lock
      • 5.4.2.2 PCI Target PCI v2.1 Delayed Read Mode
      • 5.4.2.3 PCI Target PCI Read Ahead Mode
      • 5.4.2.4 PCI Target Transfer
      • 5.4.2.5 PCI Target PCI-to-Local Address Mapping
        • 5.4.2.5.1 PCI Target Local Bus Initialization
        • 5.4.2.5.2 PCI Target PCI Initialization
        • 5.4.2.5.3 PCI Target Byte Enables (CMode)
        • 5.4.2.5.4 PCI Target Byte Enables (JMode)
          • 5.4.2.5.4.1 PCI Target Example
      • 5.4.2.6 PCI Target Priority
    • 5.4.3 Deadlock Conditions
      • 5.4.3.1 Backoff
        • 5.4.3.1.1 Software/Hardware Solution for Systems without Backoff Capability
        • 5.4.3.1.2 Preempt Solution
      • 5.4.3.2 Software Solutions to Deadlock
  • 5.5 DMA Operation
    • 5.5.1 DMA PCI Dual Address Cycle
    • 5.5.2 Block DMA Mode
      • 5.5.2.1 Block DMA PCI DualAddressCycle
    • 5.5.3 Scatter/Gather DMA Mode
      • 5.5.3.1 Scatter/Gather DMA PCI DualAddress Cycle
      • 5.5.3.2 DMA Clear Count Mode
    • 5.5.4 DMA Memory Write and Invalidate
      • 5.5.4.1 DMA Abort
    • 5.5.5 DMA Priority
    • 5.5.6 DMA Channel 0/1 Interrupts
    • 5.5.7 DMA Data Transfers
      • 5.5.7.1 Local-to-PCI Bus DMA Transfer
      • 5.5.7.2 PCI-to-Local Bus DMA Transfer
      • 5.5.7.3 DMA Unaligned Transfers
    • 5.5.8 Demand Mode DMA, Channel 0
    • 5.5.9 End of Transfer (EOT#) Input
    • 5.5.10 DMA Arbitration
    • 5.5.11 Local Bus Latency and Pause Timers
  • 5.6 C Mode Timing Diagrams
    • 5.6.1 C Mode PCI Initiator
    • 5.6.2 C Mode PCI Target
    • 5.6.3 C Mode DMA
  • 5.7 J Mode Timing Diagrams
    • 5.7.1 J Mode PCI Initiator
    • 5.7.2 J Mode PCI Target
    • 5.7.3 J Mode DMA
• 6 PCI Local Interrupts and User I/O
  • 6.1 Interrupts
    • 6.1.1 PCI Interrupts (INTA#)
    • 6.1.2 Local Interrupt Input (LINT#)
    • 6.1.3 Local Interrupt Output (LINT#)
    • 6.1.4 Master/Target Abort Interrupt
    • 6.1.5 Mailbox Registers
    • 6.1.6 Doorbell Registers
      • 6.1.6.1 Local-to-PCI Doorbell Interrupt
        • 6.1.6.1.1 M Mode Local-to-PCI Doorbell Interrupt
        • 6.1.6.1.2 C and J Modes Local-to-PCI Doorbell Interrupt
      • 6.1.6.2 PCI-to-Local Doorbell Interrupt
    • 6.1.7 Built-In Self Test Interrupt (BIST)
    • 6.1.8 DMA Channel 0/1 Interrupts
    • 6.1.9 All Modes PCI SERR# (PCI NMI)
    • 6.1.10 M Mode PCI SERR#
    • 6.1.11 Local NMI
    • 6.1.12 M Mode Local TEA# (Local NMI)
    • 6.1.13 C and J Modes Local LSERR# (Local NMI)
  • 6.2 User Input and Output
• 7 Intelligent I/O (I2O)
  • 7.1 I2O-Compatible Message Unit
    • 7.1.1 Inbound Messages
    • 7.1.2 Outbound Messages
    • 7.1.3 I2O Pointer Management
    • 7.1.4 Inbound Free List FIFO
    • 7.1.5 Inbound Post Queue FIFO
    • 7.1.6 Outbound Post Queue FIFO
    • 7.1.7 Outbound Post Queue
    • 7.1.8 Inbound Free Queue
    • 7.1.9 Outbound Free List FIFO
    • 7.1.10 I2O Enable Sequence
• 8 PCI Power Management
  • 8.1 Overview
    • 8.1.1 PCI Power Management Functional Description
    • 8.1.2 System Changes Power Mode Example
    • 8.1.3 Wake-Up Request Example
• 9 CompactPCI Hot Swap
  • 9.1 Hot Swap
    • 9.1.1 Overview
    • 9.1.2 Controlling Connection Processes
      • 9.1.2.1 Hardware Connection Control
        • 9.1.2.1.1 Board Slot Control
        • 9.1.2.1.2 Board Healthy
        • 9.1.2.1.3 Platform Reset
      • 9.1.2.2 Software Connection Control
        • 9.1.2.2.1 Ejector Switch and Blue LED
        • 9.1.2.2.2 ENUM#
        • 9.1.2.2.3 Hot Swap Control/Status Register (HS_CSR)
        • 9.1.2.2.4 Hot Swap Capabilities Register Bit Definition
• 10 PCI Vital Product Data (VPD)
  • 10.1 Overview
    • 10.1.1 VPD Capabilities Register
    • 10.1.2 VPD Serial EEPROM Partitioning
    • 10.1.3 Sequential Read Only
    • 10.1.4 Random Read and Write
• 11 Registers
  • 11.1 New Register Definitions Summary
  • 11.2 Register Address Mapping
    • 11.2.1 PCI Configuration Registers
    • 11.2.2 Local Configuration Registers
    • 11.2.3 Runtime Registers
    • 11.2.4 DMA Registers
    • 11.2.5 Messaging Queue Registers
  • 11.3 PCI Configuration Registers
  • 11.4 Local Configuration Registers
  • 11.5 Runtime Registers
  • 11.6 DMA Registers
  • 11.7 Messaging Queue Registers
• 12 Pin Description
  • 12.1 Pin Summary
  • 12.2 Pinout Common to All Bus Modes
  • 12.3 M Bus Mode Pinout
  • 12.4 C Bus Mode Pinout
  • 12.5 J Bus Mode Pinout
  • 12.6 NANDTREE Test Access Method
• 13 Electrical Specifications
  • 13.1 General Electrical Specifications
  • 13.2 Local Inputs
  • 13.3 Local Outputs
• 14 Package, Signal, and Pinout Specs
  • 14.1 176-Pin PQFP
  • 14.2 225-Pin PBGA
• A General Information
  • A.1 Ordering Instructions
  • A.2 United States andInternational Representatives, andDistributors
  • A.3 Technical Support
• Index