DATA SHEET
Preliminary specification
Supersedes data of September 1992
File under Integrated Circuits, IC01
1995 Dec 19
INTEGRATED CIRCUITS
TEA6320
Sound fader control circuit
1995 Dec 19
2
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
FEATURES
·
Source selector for four stereo and one mono inputs
·
Interface for noise reduction circuits
·
Interface for external equalizer
·
Volume, balance and fader control
·
Special loudness characteristic automatically controlled
in combination with volume setting
·
Bass and treble control
·
Mute control at audio signal zero crossing
·
Fast mute control via I
2
C-bus
·
Fast mute control via pin
·
I
2
C-bus control for all functions
·
Power supply with internal power-on reset.
GENERAL DESCRIPTION
The sound fader control circuit TEA6320 is an I
2
C-bus
controlled stereo preamplifier for car radio hi-fi sound
applications.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC
supply voltage
7.5
8.5
9.5
V
I
CC
supply current
V
CC
= 8.5 V
-
26
-
mA
V
o(rms)
maximum output voltage level
V
CC
= 8.5 V; THD
0.1%
-
2000
-
mV
G
v
voltage gain
-
86
-
+20
dB
G
step(vol)
step resolution (volume)
-
1
-
dB
G
bass
bass control
-
15
-
+15
dB
G
treble
treble control
-
12
-
+12
dB
G
step(treble)
step resolution (bass, treble)
-
1.5
-
dB
(S+N)/N
signal-plus-noise to noise ratio
V
O
= 2.0 V; G
v
= 0 dB;
unweighted
-
105
-
dB
RR
100
ripple rejection
V
r(rms)
<
200 mV; f = 100 Hz;
G
v
= 0 dB
-
76
-
dB
cs
channel separation
250 Hz
f
10 kHz; G
v
= 0 dB
90
96
-
dB
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TEA6320
SDIP32
plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
TEA6320T
SO32
plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
1995
Dec
19
3
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
POWER
SUPPLY
SOURCE
SELECTOR
VOLUME I
+20 to
-
31 dB
LOUDNESS
LEFT
BASS
LEFT
±
15 dB
TREBLE
LEFT
±
12 dB
VOLUME II
0 to
-
55 dB
BALANCE
FADER FRONT
VOLUME II
0 to
-
55 dB
BALANCE
FADER REAR
MUTE
FUNCTION
ZERO CROSS
DETECTOR
LOGIC
VOLUME I
+20 to
-
31 dB
LOUDNESS
RIGHT
BASS
RIGHT
±
15 dB
TREBLE
RIGHT
±
12 dB
VOLUME II
0 to
-
55 dB
BALANCE
FADER REAR
VOLUME II
0 to
-
55 dB
BALANCE
FADER FRONT
I
2
C-BUS
RECEIVER
21
31
2
19
16
15
11
14
22
20
18
17
13
100
µ
F
V
CC
GND
47
µ
F
9 x 220 nF
C
KIN
23
25
24
26
27
C
KVL
220 nF
8.2 nF 20 k
150 nF
2.2 k
33 nF
28
5.6 nF
TEA6320
30
29
1
32
SDA
SCL
MUTE
3
4
10
8
9
7
6
5
12
C
KVL
220 nF
8.2 nF
20 k
2.2 k
150 nF
33 nF
5.6 nF
10 nF
C
m
MED421
Vref
input
right
source
input
left
source
input
mono
source
output
right
output
left
1995 Dec 19
4
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
PINNING
SYMBOL PIN
DESCRIPTION
SDA
1
serial data input/output
GND
2
ground
OUTLR
3
output left rear
OUTLF
4
output left front
TL
5
treble control capacitor left channel or
input from an external equalizer
B2L
6
bass control capacitor left channel or
output to an external equalizer
B1L
7
bass control capacitor, left channel
IVL
8
input volume I, left control part
ILL
9
input loudness, left control part
QSL
10
output source selector, left channel
IDL
11
input D left source
MUTE
12
mute control
ICL
13
input C left source
IMO
14
input mono source
IBL
15
input B left source
IAL
16
input A left source
IAR
17
input A right source
IBR
18
input B right source
CAP
19
electronic filtering for supply
ICR
20
input C right source
V
ref
21
reference voltage (0.5V
CC
)
IDR
22
input D right source
QSR
23
output source selector right channel
ILR
24
input loudness right channel
IVR
25
input volume I, right control part
B1R
26
bass control capacitor right channel
B2R
27
bass control capacitor right channel or
output to an external equalizer
TR
28
treble control capacitor right channel
or input from an external equalizer
OUTRF
29
output right front
OUTRR
30
output right rear
V
CC
31
supply voltage
SCL
32
serial clock input
Fig.2 Pin configuration.
handbook, halfpage
TEA6320
MED422
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
B1L
B2L
TL
OUTLF
OUTLR
IAL
IBL
IMO
ICL
IDL
MUTE
QSL
ILL
IVL
ICR
IDR
Vref
IAR
IBR
CAP
QSR
ILR
IVR
B1R
B2R
TR
OUTRF
OUTRR
VCC
SCL
GND
SDA
1995 Dec 19
5
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
FUNCTIONAL DESCRIPTION
The source selector selects one of 4 stereo inputs or the
mono input. The maximum input signal voltage is
V
i(rms)
= 2 V. The outputs of the source selector and the
inputs of the following volume control parts are available at
pins 8 and 10 for the left channel and pins 23 and 25 for
the right channel. This offers the possibility of interfacing a
noise reduction system.
The volume control function is split into two sections:
volume I control block and volume II control block.
The control range of volume I is between +20 dB and
-
31 dB in steps of 1 dB. The volume II control range is
between 0 dB and
-
55 dB in steps of 1 dB. Although the
theoretical possible control range is 106 dB
(+20 to
-
86 dB), in practice a range of 86 dB (+20 to
-
66 dB) is recommended. The gain/attenuation setting of
the volume I control block is common for both channels.
The volume I control block operates in combination with
the loudness control. The filter is linear when the maximum
gain for the volume I control (+20 dB) is selected. The filter
characteristic increases automatically over a range of
32 dB down to a setting of
-
12 dB. That means the
maximum filter characteristic is obtained at
-
12 dB setting
of volume I. Further reduction of the volume does not
further influence the filter characteristic (see Fig.5). The
maximum selected filter characteristic is determined by
external components. The proposed application gives a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I
2
C-bus control
(see Table 7).
The volume I control block is followed by the bass control
block. A single external capacitor of 33 nF for each
channel in combination with internal resistors, provides the
frequency response of the bass control (see Fig.3). The
adjustable range is between
-
15 and +15 dB at 40 Hz.
Both loudness and bass control result in a maximum bass
boost of 32 dB for low volume settings.
The treble control block offers a control range between
-
12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter
characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).
The basic step width of bass and treble control is 3 dB. The
intermediate steps are obtained by switching 1.5 dB boost
and 1.5 dB attenuation steps.
The bass and treble control functions can be switched off
via I
2
C-bus. In this event the internal signal flow is
disconnected. The connections B2L and B2R are outputs
and TL and TR are inputs for inserting an external
equalizer.
The last section of the circuit is the volume II block. The
balance and fader functions are performed using the same
control blocks. This is realized by 4 independently
controllable attenuators, one for each output. The control
range of these attenuators is 55 dB in steps of 1 dB with an
additional mute step.
The circuit provides 3 mute modes:
1. Zero crossing mode mute via I
2
C-bus using
2 independent zero crossing detectors (ZCM,
see Tables 2 and 9 and Fig.16).
2. Fast mute via MUTE pin (see Fig.10).
3. Fast mute via I
2
C-bus either by general mute (GMU,
see Tables 2 and 9) or volume II block setting
(see Table 4).
The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. As the two audio channels (left and
right) are independent, two comparators are built-in to
control independent mute switches.
To avoid a large delay of mute switching when very low
frequencies are processed, the maximum delay time is
limited to typically 100 ms by an integrated timing circuit
and an external capacitor (C
m
= 10 nF, see Fig.10). This
timing circuit is triggered by reception of a new data word
for the switch function which includes the GMU bit. After a
discharge and charge period of an external capacitor the
muting switch follows the GMU bit if no zero crossing was
detected during that time.
The mute function can also be controlled externally. If the
mute pin is switched to ground all outputs are muted
immediately (hardware mute). This mute request
overwrites all mute controls via the I
2
C-bus for the time the
pin is held LOW. The hardware mute position is not stored
in the TEA6320.
For the turn on/off behaviour the following explanation is
generally valid. To avoid AF output caused by the input
signal coming from preceding stages, which produces
output during drop of V
CC
, the mute has to be set, before
the V
CC
will drop. This can be achieved by I
2
C-bus control
or by grounding the MUTE pin.
For use where is no mute in the application before turn off,
a supply voltage drop of more than 1
×
V
BE
will result in a
mute during the voltage drop.
1995 Dec 19
6
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
The power supply should include a V
CC
buffer capacitor,
which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after certain time. A 4.7 k
resistor
discharges the V
CC
buffer capacitor, because the internal
current of the IC does not discharge it completely.
The hardware mute function is favourable for use in Radio
Data System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Human body model: C = 100 pF; R = 1.5 k
; V
2 kV. Charge device model: C = 200 pF; R = 0
; V
500 V.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
0
10
V
V
n
voltage at all pins except pin 2
referenced to GND (pin 2)
0
V
CC
V
T
amb
operating ambient temperature
-
40
+85
°
C
T
stg
storage temperature
-
65
+150
°
C
V
es
electrostatic handling
note 1
1995 Dec 19
7
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
CHARACTERISTICS
V
CC
= 8.5 V; R
S
= 600
; R
L
= 10 k
; C
L
= 2.5 nF; AC coupled; f = 1 kHz; T
amb
= 25
°
C; gain control G
v
= 0 dB; bass
linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC
supply voltage
7.5
8.5
9.5
V
I
CC
supply current
-
26
33
mA
V
DC
internal DC voltage at inputs and
outputs
3.83
4.25
4.68
V
V
ref
internal reference voltage at pin 21
-
4.25
-
V
G
v(max)
maximum voltage gain
R
S
= 0
; R
L
=
19
20
21
dB
V
o(rms)
output voltage level for
P
max
at the power output stage
THD
0.5%; see Fig.11
-
2000
-
mV
start of clipping
THD = 1%
2300
-
-
mV
R
L
= 2 k
; C
L
= 10 nF;
THD = 1%
2000
-
-
mV
V
i(rms)
input sensitivity
V
o
= 2000 mV; G
v
= 20 dB
-
200
-
mV
f
ro
roll-off frequency
C
KIN
= 220 nF;
C
KVL
= 220 nF; Z
i
= Z
i(min)
low frequency (
-
1 dB)
60
-
-
Hz
low frequency (
-
3 dB)
30
-
-
Hz
high frequency (
-
1 dB)
20000
-
-
Hz
C
KIN
= 470 nF;
C
KVL
= 100 nF; Z
i
= Z
i(typ)
low frequency (
-
3 dB)
17
-
-
Hz
cs
channel separation
V
i
= 2 V; frequency range
250 Hz to 10 kHz
90
96
-
dB
THD
total harmonic distortion
frequency range
20 Hz to 12.5 kHz
V
i
= 100 mV; G
v
= 20 dB
-
0.1
-
%
V
i
= 1 V; G
v
= 0 dB
-
0.05
0.15
%
V
i
= 2 V; G
v
= 0 dB
-
0.1
-
%
V
i
= 2 V; G
v
=
-
10 dB
-
0.1
-
%
RR
ripple rejection
V
r(rms)
<
200 mV
f = 100 Hz
70
76
-
dB
f = 40 Hz to 12.5 kHz
-
66
-
dB
(S+N)/N
signal-plus-noise to noise ratio
unweighted;
20 Hz to 20 kHz (RMS);
V
o
= 2.0 V; see Figs 6 and 7
-
105
-
dB
CCIR468-2 weighted; quasi
peak; V
o
= 2.0 V
G
v
= 0 dB
-
95
-
dB
G
v
= 12 dB
-
88
-
dB
G
v
= 20 dB
-
81
-
dB
1995 Dec 19
8
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
P
no(rms)
noise output power (RMS value)
only contribution of TEA6320;
power amplifier for 6 W
mute position; note 1
-
-
10
nW
ct
crosstalk
between bus
inputs and signal outputs
note 2
-
110
-
dB
Source selector
Z
i
input impedance
25
35
45
k
S
input isolation of one selected
source to any other input
f = 1 kHz
-
105
-
dB
f = 12.5 kHz
-
95
-
dB
V
i(rms)
maximum input voltage
(RMS value)
THD
<
0.5%; V
CC
= 8.5 V
-
2.15
-
V
THD
<
0.5%; V
CC
= 7.5 V
-
1.8
-
V
V
offset
DC offset voltage at source
selector output by selection of any
inputs
-
-
10
mV
Z
o
output impedance
-
80
120
R
L
output load resistance
10
-
-
k
C
L
output load capacity
0
-
2500
pF
G
v
voltage gain, source selector
-
0
-
dB
Control part (source selector disconnected; source resistance 600
)
Z
i
input impedance volume input
100
150
200
k
input impedance loudness input
25
33
40
k
Z
o
output impedance
-
80
120
R
L
output load resistance
2
-
-
k
C
L
output load capacity
0
-
10
nF
R
DCL
DC load resistance at output to
ground
4.7
-
-
k
V
i(rms)
maximum input voltage
(RMS value)
THD
<
0.5%
-
2.15
-
V
V
no
noise output voltage
CCIR468-2 weighted; quasi
peak
G
v
= 20 dB
-
110
220
µ
V
G
v
= 0 dB
-
33
50
µ
V
G
v
=
-
66 dB
-
13
22
µ
V
mute position
-
10
-
µ
V
CR
tot
total continuous control range
-
106
-
dB
recommended control range
-
86
-
dB
G
step
step resolution
-
1
-
dB
step error between any adjoining
step
-
-
0.5
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
20
V
bus p
p
(
)
V
o rms
(
)
---------------------------
log
1995 Dec 19
9
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
G
a
attenuator set error
G
v
= +20 to
-
50 dB
-
-
2
dB
G
v
=
-
51 to
-
66 dB
-
-
3
dB
G
t
gain tracking error
G
v
= +20 to
-
50 dB
-
-
2
dB
MUTE
att
mute attenuation
see Fig.10
100
110
-
dB
V
offset
DC step offset between any
adjoining step
G
v
= 0 to
-
66 dB
-
0.2
10
mV
G
v
= 20 to 0 dB
-
2
15
mV
DC step offset between any step to
mute
G
v
= 0 to
-
66 dB
-
-
10
mV
Volume I control and loudness
CR
vol
continuous volume control range
-
51
-
dB
G
v
voltage gain
-
31
-
+20
dB
G
step
step resolution
-
1
-
dB
L
Bmax
maximum loudness boost
loudness on; referred to
loudness off; boost is
determined by external
components
f = 40 Hz
-
17
-
dB
f = 10 kHz
-
4.5
-
dB
Bass control
G
bass
bass control, maximum boost
f = 40 Hz
14
15
16
dB
maximum attenuation
f = 40 Hz
14
15
16
dB
G
step
step resolution (toggle switching)
f = 40 Hz
-
1.5
-
dB
step error between any adjoining
step
f = 40 Hz
-
-
0.5
dB
V
offset
DC step offset in any bass position
-
-
20
mV
Treble control
G
treble
treble control, maximum boost
f = 15 kHz
11
12
13
dB
maximum attenuation
f = 15 kHz
11
12
13
dB
maximum boost
f
>
15 kHz
-
-
15
dB
G
step
step resolution (toggle switching)
f = 15 kHz
-
1.5
-
dB
step error between any adjoining
step
f = 15 kHz
-
-
0.5
dB
V
offset
DC step offset in any treble
position
-
-
10
mV
Volume II, balance and fader control
CR
continuous attenuation fader and
volume control range
53.5
55
56.5
dB
G
step
step resolution
-
1
2
dB
attenuation set error
-
-
1.5
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1995 Dec 19
10
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Notes to the characteristics
1. The indicated values for output power assume a 6 W power amplifier at 4
with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.
2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).
3. The AC characteristics are in accordance with the I
2
C-bus specification. This specification,
"The I
2
C-bus and how to
use it", can be ordered using the code 9398 393 40011.
Mute function (see Fig.10)
H
ARDWARE MUTE
V
sw
mute switch level (2
×
V
BE
)
-
1.45
-
V
mute active
V
swLOW
input level
-
-
1.0
V
I
i
input current
V
swLOW
= 1 V
-
300
-
-
µ
A
mute passive: level internally defined
V
swHIGH
saturation voltage
-
-
V
CC
V
t
d(mute)
delay until mute passive
-
-
0.5
ms
Z
ERO CROSSING MUTE
I
d
discharge current
0.3
0.6
1.2
µ
A
I
ch
charge current
-
300
-
150
-
µ
A
V
swDEL
delay switch level (3
×
V
BE
)
-
2.2
-
V
t
d
delay time
C
m
= 10 nF
-
100
-
ms
V
wind
window for audio signal zero
crossing detection
-
30
40
mV
Muting at power supply drop
V
CCdrop
supply drop for mute active
-
V
19
-
0.7
-
V
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I
2
C-bus receiver is in
reset position)
V
CC
increasing supply voltage start of
reset
-
-
2.5
V
end of reset
5.2
6.5
7.2
V
decreasing supply voltage start of
reset
4.2
5.5
6.2
V
Digital part (I
2
C-bus pins); note 3
V
iH
HIGH level input voltage
3
-
9.5
V
V
iL
LOW level input voltage
-
0.3
-
+1.5
V
I
iH
HIGH level input current
-
10
-
+10
µ
A
I
iL
LOW level input current
-
10
-
+10
µ
A
V
oL
LOW level output voltage
I
L
= 3 mA
-
-
0.4
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1995 Dec 19
11
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
I
2
C-BUS PROTOCOL
I
2
C-bus format
Notes
1. S = START condition.
2. SLAVE ADDRESS (MAD) = 1000 0000.
3. A = acknowledge, generated by the slave.
4. SUBADDRESS (SAD), see Table 1.
5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is
performed.
6. P = STOP condition.
Table 1
Second byte after MAD
Note
1. Significant subaddress.
S
(1)
SLAVE ADDRESS
(2)
A
(3)
SUBADDRESS
(4)
A
(3)
DATA
(5)
A
(3)
P
(6)
FUNCTION
BIT
MSB
LSB
7
6
5
4
3
2
(1)
1
(1)
0
(1)
Volume/loudness
V
0
0
0
0
0
0
0
0
Fader front right
FFR
0
0
0
0
0
0
0
1
Fader front left
FFL
0
0
0
0
0
0
1
0
Fader rear right
FRR
0
0
0
0
0
0
1
1
Fader rear left
FRL
0
0
0
0
0
1
0
0
Bass
BA
0
0
0
0
0
1
0
1
Treble
TR
0
0
0
0
0
1
1
0
Switch
S
0
0
0
0
0
1
1
1
1995 Dec 19
12
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 2
Definition of third byte after MAD and SAD
Notes
1. Zero crossing mode.
2. Switch loudness on/off.
3. Volume control.
4. Don't care bits (logic 1 during testing).
5. Fader control front right.
6. Fader control front left.
7. Fader control rear right.
8. Fader control rear left.
9. Bass control.
10. Treble control.
11. Mute control for all outputs (general mute).
12. Source selector control.
FUNCTION
BIT
MSB
LSB
7
6
5
4
3
2
1
0
Volume/loudness
V
ZCM
(1)
LOFF
(2)
V5
(3)
V4
(3)
V3
(3)
V2
(3)
V1
(3)
V0
(3)
Fader front right
FFR
X
(4)
X
(4)
FFR5
(5)
FFR4
(5)
FFR3
(5)
FFR2
(5)
FFR1
(5)
FFR0
(5)
Fader front left
FFL
X
(4)
X
(4)
FFL5
(6)
FFL4
(6)
FFL3
(6)
FFL2
(6)
FFL1
(6)
FFL0
(6)
Fader rear right
FRR
X
(4)
X
(4)
FRR5
(7)
FRR4
(7)
FRR3
(7)
FRR2
(7)
FRR1
(7)
FRR0
(7)
Fader rear left
FRL
X
(4)
X
(4)
FRL5
(8)
FRL4
(8)
FRL3
(8)
FRL2
(8)
FRL1
(8)
FRL0
(8)
Bass
BA
X
(4)
X
(4)
X
(4)
BA4
(9)
BA3
(9)
BA2
(9)
BA1
(9)
BA0
(9)
Treble
TR
X
(4)
X
(4)
X
(4)
TR4
(10)
TR3
(10)
TR2
(10)
TR1
(10)
TR0
(10)
Switch
S
GMU
(11)
X
(4)
X
(4)
X
(4)
X
(4)
SC2
(12)
SC1
(12)
SC0
(12)
1995 Dec 19
13
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 3
Volume I setting
G
v
(dB)
DATA
V5
V4
V3
V2
V1
V0
Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from
+20 to
-
11 dB
+20
1
1
1
1
1
1
+19
1
1
1
1
1
0
+18
1
1
1
1
0
1
+17
1
1
1
1
0
0
+16
1
1
1
0
1
1
+15
1
1
1
0
1
0
+14
1
1
1
0
0
1
+13
1
1
1
0
0
0
+12
1
1
0
1
1
1
+11
1
1
0
1
1
0
+10
1
1
0
1
0
1
+9
1
1
0
1
0
0
+8
1
1
0
0
1
1
+7
1
1
0
0
1
0
+6
1
1
0
0
0
1
+5
1
1
0
0
0
0
+4
1
0
1
1
1
1
+3
1
0
1
1
1
0
+2
1
0
1
1
0
1
+1
1
0
1
1
0
0
0
1
0
1
0
1
1
-
1
1
0
1
0
1
0
-
2
1
0
1
0
0
1
-
3
1
0
1
0
0
0
-
4
1
0
0
1
1
1
-
5
1
0
0
1
1
0
-
6
1
0
0
1
0
1
-
7
1
0
0
1
0
0
-
8
1
0
0
0
1
1
-
9
1
0
0
0
1
0
-
10
1
0
0
0
0
1
-
11
1
0
0
0
0
0
1995 Dec 19
14
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Loudness characteristic is constant in a range from
-
11 dB to
-
31 dB
-
12
0
1
1
1
1
1
-
13
0
1
1
1
1
0
-
14
0
1
1
1
0
1
-
15
0
1
1
1
0
0
-
16
0
1
1
0
1
1
-
17
0
1
1
0
1
0
-
18
0
1
1
0
0
1
-
19
0
1
1
0
0
0
-
20
0
1
0
1
1
1
-
21
0
1
0
1
1
0
-
22
0
1
0
1
0
1
-
23
0
1
0
1
0
0
-
24
0
1
0
0
1
1
-
25
0
1
0
0
1
0
-
26
0
1
0
0
0
1
-
27
0
1
0
0
0
0
-
28
0
0
1
1
1
1
-
29
0
0
1
1
1
0
-
30
0
0
1
1
0
1
-
31
0
0
1
1
0
0
Repetition of steps in a range from
-
28 dB to
-
31 dB
-
28
0
0
1
0
1
1
-
29
0
0
1
0
1
0
-
30
0
0
1
0
0
1
-
31
0
0
1
0
0
0
-
28
0
0
0
1
1
1
-
29
0
0
0
1
1
0
-
30
0
0
0
1
0
1
-
31
0
0
0
1
0
0
-
28
0
0
0
0
1
1
-
29
0
0
0
0
1
0
-
30
0
0
0
0
0
1
-
31
0
0
0
0
0
0
G
v
(dB)
DATA
V5
V4
V3
V2
V1
V0
1995 Dec 19
15
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 4
Volume II setting (fader and balance); note 1
G
v
(dB)
DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
0
1
1
1
1
1
1
-
1
1
1
1
1
1
0
-
2
1
1
1
1
0
1
-
3
1
1
1
1
0
0
-
4
1
1
1
0
1
1
-
5
1
1
1
0
1
0
-
6
1
1
1
0
0
1
-
7
1
1
1
0
0
0
-
8
1
1
0
1
1
1
-
9
1
1
0
1
1
0
-
10
1
1
0
1
0
1
-
11
1
1
0
1
0
0
-
12
1
1
0
0
1
1
-
13
1
1
0
0
1
0
-
14
1
1
0
0
0
1
-
15
1
1
0
0
0
0
-
16
1
0
1
1
1
1
-
17
1
0
1
1
1
0
-
18
1
0
1
1
0
1
-
19
1
0
1
1
0
0
-
20
1
0
1
0
1
1
-
21
1
0
1
0
1
0
-
22
1
0
1
0
0
1
-
23
1
0
1
0
0
0
-
24
1
0
0
1
1
1
-
25
1
0
0
1
1
0
-
26
1
0
0
1
0
1
-
27
1
0
0
1
0
0
-
28
1
0
0
0
1
1
-
29
1
0
0
0
1
0
-
30
1
0
0
0
0
1
-
31
1
0
0
0
0
0
-
32
0
1
1
1
1
1
-
33
0
1
1
1
1
0
-
34
0
1
1
1
0
1
1995 Dec 19
16
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Note
1. For a particular range the data is always the same, only the subaddress changes.
-
35
0
1
1
1
0
0
-
36
0
1
1
0
1
1
-
37
0
1
1
0
1
0
-
38
0
1
1
0
0
1
-
39
0
1
1
0
0
0
-
40
0
1
0
1
1
1
-
41
0
1
0
1
1
0
-
42
0
1
0
1
0
1
-
43
0
1
0
1
0
0
-
44
0
1
0
0
1
1
-
45
0
1
0
0
1
0
-
46
0
1
0
0
0
1
-
47
0
1
0
0
0
0
-
48
0
0
1
1
1
1
-
49
0
0
1
1
1
0
-
50
0
0
1
1
0
1
-
51
0
0
1
1
0
0
-
52
0
0
1
0
1
1
-
53
0
0
1
0
1
0
-
54
0
0
1
0
0
1
-
55
0
0
1
0
0
0
mute
0
0
0
1
1
1
mute
0
0
0
1
1
0
mute
0
0
0
1
0
1
mute
0
0
0
1
0
0
mute
0
0
0
0
1
1
mute
0
0
0
0
1
0
mute
0
0
0
0
0
1
mute
0
0
0
0
0
0
G
v
(dB)
DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
1995 Dec 19
17
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 5
Bass setting
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.5 dB boost and 1.5 dB attenuation.
3. The last four bass control data words mute the bass response.
4. The last bass control and treble control data words (00000) enable the external equalizer connection.
G
bass
(dB)
DATA
BA4
BA3
BA2
BA1
BA0
+15.0
1
1
1
1
1
+13.5
1
1
1
1
0
+15.0
1
1
1
0
1
+13.5
1
1
1
0
0
+15.0
1
1
0
1
1
+13.5
1
1
0
1
0
+12.0
1
1
0
0
1
+10.5
1
1
0
0
0
+9.0
1
0
1
1
1
+7.5
1
0
1
1
0
+6.0
1
0
1
0
1
+4.5
1
0
1
0
0
+3.0
1
0
0
1
1
+1.5
1
0
0
1
0
0
(1)
1
0
0
0
1
0
(2)
1
0
0
0
0
-
1.5
0
1
1
1
1
-
3.0
0
1
1
1
0
-
4.5
0
1
1
0
1
-
6.0
0
1
1
0
0
-
7.5
0
1
0
1
1
-
9.0
0
1
0
1
0
-
10.5
0
1
0
0
1
-
12.0
0
1
0
0
0
-
13.5
0
0
1
1
1
-
15.0
0
0
1
1
0
-
13.5
0
0
1
0
1
-
15.0
0
0
1
0
0
note 3
0
0
0
1
1
note 3
0
0
0
1
0
note 3
0
0
0
0
1
notes 3 and 4
0
0
0
0
0
1995 Dec 19
18
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 6
Treble setting
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.5 dB boost and 1.5 dB attenuation.
3. The last eight treble control data words select treble output.
4. The last treble control and bass control data words (00000) enable the external equalizer connection.
G
treble
(dB)
DATA
TR4
TR3
TR2
TR1
TR0
+12.0
1
1
1
1
1
+10.5
1
1
1
1
0
+12.0
1
1
1
0
1
+10.5
1
1
1
0
0
+12.0
1
1
0
1
1
+10.5
1
1
0
1
0
+12.0
1
1
0
0
1
+10.5
1
1
0
0
0
+9.0
1
0
1
1
1
+7.5
1
0
1
1
0
+6.0
1
0
1
0
1
+4.5
1
0
1
0
0
+3.0
1
0
0
1
1
+1.5
1
0
0
1
0
0
(1)
1
0
0
0
1
0
(2)
1
0
0
0
0
-
1.5
0
1
1
1
1
-
3.0
0
1
1
1
0
-
4.5
0
1
1
0
1
-
6.0
0
1
1
0
0
-
7.5
0
1
0
1
1
-
9.0
0
1
0
1
0
-
10.5
0
1
0
0
1
-
12.0
0
1
0
0
0
note 3
0
0
1
1
1
note 3
0
0
1
1
0
note 3
0
0
1
0
1
note 3
0
0
1
0
0
note 3
0
0
0
1
1
note 3
0
0
0
1
0
note 3
0
0
0
0
1
notes 3 and 4
0
0
0
0
0
1995 Dec 19
19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Table 7
Loudness setting
Table 8
Selected input
Note
1. X = don't care bits (logic 1 during testing).
CHARACTERISTIC
DATA LOFF
With loudness
0
Linear
1
FUNCTION
DATA
SC2
SC1
SC0
Stereo inputs IAL and IAR
1
1
1
Stereo inputs IBL and IBR
1
1
0
Stereo inputs ICL and ICR
1
0
1
Stereo inputs IDL and IDR
1
0
0
Mono input IMO
0
X
(1)
X
(1)
Table 9
Mute mode
FUNCTION
DATA
GMU
ZCM
Direct mute off
0
0
Mute off delayed until the next zero
crossing
0
1
Direct mute
1
0
Mute delayed until the next zero
crossing
1
1
1995 Dec 19
20
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Fig.3 Bass control.
handbook, full pagewidth
-
18
-
12
-
6
18
10
4
10
3
10
2
10
6
12
0
f (Hz)
Gbass
(dB)
MED423
Fig.4 Treble control.
handbook, full pagewidth
-
15
-
10
-
5
15
10
5
10
4
10
3
2
10
5
10
0
f (Hz)
Gtreble
(dB)
MED424
1995 Dec 19
21
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Fig.5 Volume control with loudness (including low roll-off frequency).
handbook, full pagewidth
20
0
10
5
MED425
10
4
10
3
10
2
10
-
10
-
20
-
30
-
40
10
f (Hz)
Gv
(dB)
Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak.
(1) V
i
= 2.0 V.
(2) V
i
= 0.5 V.
(3) V
i
= 0.2 V.
handbook, full pagewidth
50
100
1
10
10
-
1
10
-
2
10
-
3
10
-
4
MED426
60
70
80
90
Po (W)
S/N
(dB)
(1)
(2)
(3)
1995 Dec 19
22
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Fig.7 Signal-to-noise ratio; V
i
= 2 V; P
max
= 6 W.
(1) Unweighted RMS.
(2) CCIR468-2 RMS.
(3) CCIR468-2 quasi peak.
handbook, full pagewidth
60
110
1
10
10
-
1
10
-
2
10
-
3
10
-
4
MED427
70
80
90
100
Po (W)
S/N
(dB)
(1)
(2)
(3)
Fig.8 Noise output voltage; CCIR468-2, quasi peak.
handbook, full pagewidth
30
200
150
50
0
-
70
-
50
-
30
-
10
10
MED428
100
gain (dB)
noise
(
µ
V)
(1)
(2)
Stereo/mono inputs.
(1) Loudness on.
(2) Loudness off.
1995 Dec 19
23
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
-
60
-
80
-
100
-
120
-
140
MED429
f (Hz)
(dB)
10
2
10
3
2 x 10
3
5 x 10
3
10
4
2 x 10
4
50
20
500
200
Fig.9 Muting.
1995 Dec 19
24
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Fig.10 Mute function diagram.
(1) Typically 2.2 V; referenced to 3
×
V
BE
.
handbook, full pagewidth
MED430
TEA6320
ICH =
-
150
µ
A
ID = 0.6
µ
A
Cm = 10 nF
hardware mute switch
mute pin 12
2.2
1.45
0
-
150
0.5 ms delay until
mute passive
100 ms
t (ms)
U
(V)
VCC
8.5
delay switch
level
mute switch
level
I
(
µ
A)
(1)
zero crossing
mute start
end of delay
hard mute
on
hard mute
off
1995 Dec 19
25
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
If the 20 dB gain is not required for the maximum volume
position, it will be an advantage to use the maximum boost
gain and then increased attenuation in the last section,
Volume II.
Therefore the loudness will be at the correct place and a
lower noise and offset voltage will be achieved.
Fig.11 Level diagram.
handbook, halfpage
Vo = 2 V for P(max)
POWER STAGE
G = 20 dB
TEA6320
P(max) = 100 W at 4
VI(min) = 200 mV
MBE899
handbook, halfpage
Vo = 1 V for P(max)
POWER STAGE
G = 26 dB
TEA6320
P(max) = 100 W at 4
VI(min) = 200 mV
MED431
a.
b.
a. Gain volume I = 20 dB (G
v(max)
); gain volume II = 0 dB; fader and balance range = 55 dB.
b. Gain volume I = 20 dB (G
v(max)
); gain volume II =
-
6 dB global setting; fader and balance range now 49 dB, previously 55 dB.
1995 Dec 19
26
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
16
15
13
11
14
17
18
20
22
2
19
21
30
29
4
3
31
TEA6320
+
V
CC
8.5 V
4.7 k
9
×
220 nF
9
×
600
inputs
+8.5 V to
oscilloscope
outputs to
oscilloscope
4
×
4.7
µ
F
4
×
10 k
V
P
100
47
470
µ
F
µ
F
µ
F
MED432
Fig.12 Turn-on/off power supply circuit diagram.
Fig.13 Turn-on/off behaviour.
(1) V
CC
.
(2) V
O
.
handbook, full pagewidth
5
10
0
0
1
2
3
4
MED433
2
4
6
8
t (s)
(V)
(1)
(2)
1995 Dec 19
27
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Fig.14 Test circuit for power supply ripple rejection (RR).
handbook, full pagewidth
TEA6320
input A to D left and right
and input mono
output right
output left
front and rear
10
8
7
6
5
12
32
1
21
31
2
19
23
25
26
27
28
V
P
10 k
0.2 V (RMS)
1000
µ
F
47
µ
F
0.1
µ
F
V
CC
= 8.5 V
100
µ
F
600
220 nF
220 nF
33 nF
5.6 nF
SCL
SDA
4.7
µ
F
V
O
5.6 nF
33 nF
220 nF
10 nF
MED434
Fig.15 Test circuit for channel separation (
cs
).
handbook, full pagewidth
MED435
output left
output right
front and rear
V
p
47
µ
F
0.1
µ
F
V
CC
= 8.5 V
100
µ
F
600
220 nF
SCL
SDA
4.7
µ
F
V
O
5.6 nF
33 nF
220 nF
V
i
220 nF
470
µ
F
input A to D right and left
TEA6320
input A to D left and right
and input mono
10
8
7
6
5
12
32
1
21
31
2
19
23
25
26
27
28
220 nF
33 nF
5.6 nF
10 nF
1995 Dec 19
28
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Selection of input signals by using the zero crossing
mute mode
A selection from input A (IAL) to input B (IBL) left sources
produces a modulation click depending on the difference
of the signal values at the time of switching.
At t
1
the maximum possible difference between signals is
7 V(p-p) (see Fig. 16) and gives a large click. Using the
cross detector no modulation click is audible.
For example: The selection is enabled at t
1
, the
microcontroller sets the zero cross bit (ZCM = 1) and then
the mute bit (GMU = 1) via the I
2
C-bus. The output signal
follows the input A signal, until the next zero crossing
occurs and then activates mute.
After a fixed delay time at t
2
, the microcontroller sends the
bits for input switching and mute inactive.
The output signal remains muted until the next signal zero
crossing of input B (IBL) occurs, and then follows that
signal.
The delay time t
2
-
t
1
is e.g. 40 ms. Therefore the capacity
C
m
= 3.3 nF. The zero cross function is working at the
lowest frequency of 40 Hz determined by the C
m
capacitor.
Fig.16 Zero cross function; only one channel shown.
handbook, full pagewidth
V
t
t1
4
0
-
1
-
2
-
3
-
4
1
2
3
t2
MED436
(1)
(2)
(3)
(1) Input A (IAL).
(2) Output.
(3) Input B (IBL).
1995 Dec 19
29
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Loudness filter calculation example
Figure 17 shows the basic loudness circuit with an
external low-pass filter application. R1 allows an
attenuation range of 21 dB while the boost is determined
by the gain stage V
2
. Both result in a loudness control
range of +20 to
-
12 dB.
Defining f
ref
as the frequency where the level does not
change while switching loudness on/off. The external
resistor R3 for f
ref
can be calculated as:
. With G
v
=
-
21 dB and R1 = 33 k
,
R3 = 3.2 k
is generated.
For the low-pass filter characteristic the value of the
external capacitor C1 can be determined by setting a
specific boost for a defined frequency and referring the
gain to G
v
at f
ref
as indicated above.
For example: 3 dB boost at f = 1 kHz
G
v
= G
v(ref)
+ 3 dB =
-
18 dB; f = 1 kHz and C1 = 100 nF.
If a loudness characteristic with additional high frequency
boost is desired, an additional high-pass section has to be
included in the external filter circuit as indicated in the
block diagram. A filter configuration that provides
AC coupling avoids offset voltage problems.
R3
R1
10
G
v
20
-------
1
10
G
v
20
-------
---------------------
=
1
j
C1
(
)
---------------------
R1
R3
+
(
)
10
G
v
20
-------
R3
×
1
10
G
v
20
-------
--------------------------------------------------------------
=
Fig.17 Basic loudness circuit.
handbook, halfpage
MED437
V1
V2
R1
R3
C1
CKVL
R2
0 dB
33 k
8
9
1995 Dec 19
30
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
INTERNAL PIN CONFIGURATIONS
Values shown in Figs 18 to 30 are typical DC values;
V
CC
= 8.5 V.
MBE900
5 V
1.8 k
1
Fig.18 Pin 1: SDA (I
2
C-bus data).
MBE901
4.25 V
80
+
3
Fig.19 Pins 3, 4, 29, 30: output signals.
MBE902
4.25 V
2.4 k
+
+
5
Fig.20 Pins 5 and 28: treble control capacitors.
MBE903
+
4.25 V
80
6
Fig.21 Pins 6 and 27: bass control capacitor outputs.
1995 Dec 19
31
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
MBE904
4.16 k
9.4 k
4.25 V
4.25 V
+
7
Fig.22 Pins 7 and 26: bass control capacitor inputs.
MED438
4.25 V
+
150 k
4.25 V
8
Fig.23 Pins 8 and 25: input volume 1, control part.
MBE905
9
4.25 V
1.12 k
+
Fig.24 Pins 9 and 24: input loudness, control part.
MBE906
+
4.25 V
80
10
Fig.25 Pins 10 and 23: output source selector.
1995 Dec 19
32
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
MBE907
+
4.25 V
35 k
4.25 V
11
Fig.26 Pins 11, 13 to 18, 20, 22: inputs.
MBE908
+
8.5 V
constant
2.2 V
1.3 k
4.5 k
maximum
200
µ
A
0.6
µ
A
constant
12
Fig.27 Pin 12: mute control.
Fig.28 Pin 19: filtering for supply; pin 21: reference voltage.
MHA063
19
21
+
+
4.7 k
300
8.4 V
5 k
4.25 V
3.4 k
3.4 k
MBE909
31
apply +8.5 V to this pin
Fig.29 Pin 31: supply voltage.
MED440
32
5 V
1.8 k
Fig.30 Pin 32: SCL (I
2
C-bus clock).
1995 Dec 19
33
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
PACKAGE OUTLINES
UNIT
b
1
c
E
e
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
DIMENSIONS (mm are the original dimensions)
SOT232-1
92-11-17
95-02-04
b
max.
w
M
E
e
1
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
3.2
2.8
0.18
1.778
10.16
10.7
10.2
12.2
10.5
1.6
4.7
0.51
3.8
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
32
1
17
16
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)
D
(1)
Z
A
max.
1
2
A
min.
A
max.
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
1995 Dec 19
34
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.10
0.25
0.01
1.4
0.055
0.3
0.1
2.45
2.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4
1.27
10.65
10.00
1.2
1.0
0.95
0.55
8
0
o
o
0.25
0.1
0.004
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT287-1
(1)
0.012
0.004
0.096
0.086
0.02
0.01
0.050
0.047
0.039
0.419
0.394
0.30
0.29
0.81
0.80
0.011
0.007
0.037
0.022
0.01
0.01
0.043
0.016
w
M
b
p
D
H
E
Z
e
c
v
M
A
X
A
y
32
17
16
1
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
E
pin 1 index
0
5
10 mm
scale
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
95-01-25
97-05-22
1995 Dec 19
35
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
SDIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260
°
C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300
°
C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400
°
C, contact may be up to 5 seconds.
SO
R
EFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
°
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
°
C.
W
AVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
·
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
·
The longitudinal axis of the package footprint must be
parallel to the solder flow.
·
The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
°
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
°
C within
6 seconds. Typical dwell time is 4 seconds at 250
°
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
°
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
°
C.
1995 Dec 19
36
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Dec 19
37
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
NOTES
1995 Dec 19
38
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
NOTES
1995 Dec 19
39
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
NOTES
Philips Semiconductors a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
Tel. (31)40-2783749, Fax. (31)40-2788399
Brazil: Rua do Rocio 220 - 5
th
floor, Suite 51,
CEP: 04552-903-SĂO PAULO-SP, Brazil,
P.O. Box 7383 (01064-970),
Tel. (011)821-2333, Fax. (011)829-1849
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:
Tel. (800) 234-7381, Fax. (708) 296-8556
Chile: Av. Santa Maria 0760, SANTIAGO,
Tel. (02)773 816, Fax. (02)777 6730
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. (852)2319 7888, Fax. (852)2319 7700
Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,
77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,
Fax. (571)217 4549
Denmark: Prags Boulevard 80, PB 1919, DK-2300
COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (358)0-615 800, Fax. (358)0-61580 920
France: 4 Rue du Port-aux-Vins, BP317,
92156 SURESNES Cedex,
Tel. (01)4099 6161, Fax. (01)4099 6427
Germany: P.O. Box 10 51 40, 20035 HAMBURG,
Tel. (040)23 53 60, Fax. (040)23 53 63 00
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01)4894 339/4894 911, Fax. (01)4814 240
India: Philips INDIA Ltd, Shivsagar Estate, A Block,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. (022)4938 541, Fax. (022)4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)7640 000, Fax. (01)7640 200
Italy: PHILIPS SEMICONDUCTORS S.r.l.,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5130, Fax. (03)3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,
Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. (040)2783749, Fax. (040)2788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474
Portugal: PHILIPS PORTUGUESA, S.A.,
Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)4163160/4163333, Fax. (01)4163174/4163366
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: S.A. PHILIPS Pty Ltd.,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430, Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 42 43
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (01)488 2211, Fax. (01)481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (66) 2 745-4090, Fax. (66) 2 398-0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0 212)279 27 70, Fax. (0212)282 67 07
Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165,
252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991
United Kingdom: Philips Semiconductors LTD.,
276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181)730-5000, Fax. (0181)754-8421
United States: 811 East Arques Avenue, SUNNYVALE,
CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825
SCDS47
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/1100/02/pp40
Date of release: 1995 Dec 19
Document order number:
9397 750 00533
PDF 
ZIP