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Part Number PCA9516

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Philips
Semiconductors
PCA9516
5-channel I
2
C hub
Product data
Supersedes data of 2002 Mar 01
2002 May 13
INTEGRATED CIRCUITS
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2
2002 May 13
853­2234 28185
DESCRIPTION
The PCA9516 is a BiCMOS integrated circuit intended for
application in I
2
C and SMBus systems.
While retaining all the operating modes and features of the I
2
C
system, it permits extension of the I
2
C bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.
The I
2
C bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9516 enables the system
designer to divide the bus into five segments off of a hub where any
segment to segment transition sees only one repeater delay.
It can also be used to run different buses at 5 V and 3.3 V or
400 kHz and 100 kHz buses where the 100 kHz bus is isolated
when 400 kHz operation of the other bus is required.
FEATURES
·
5 channel, bi-directional buffer
·
I
2
C-bus and SMBus compatible
·
Active high individual repeater enable input
·
Open-drain input/outputs
·
Lock-up free operation
·
Supports arbitration and clock stretching across the repeater
·
Accommodates standard mode and fast mode I
2
C devices and
multiple masters
·
Powered-off high impedance I
2
C pins
·
Operating supply voltage range of 3.0 V to 3.6 V
·
5 V tolerant I
2
C and enable pins
·
0 to 400 kHz clock frequency
1
·
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
·
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA.
·
Package offerings: SO and TSSOP
PIN CONFIGURATION
1
2
3
4
SCL0
SDA1
SCL1
EN4
SDA4
SCL4
13
14
15
16
VCC
SDA0
SU01395
5
6
7
8
EN1
GND
SDA2
SDA3
SCL3
EN2
9
10
11
12
EN3
SCL2
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
SYMBOL
FUNCTION
1
SCL0
Serial clock bus 0
2
SDA0
Serial data bus 0
3
SCL1
Serial clock bus 1
4
SDA1
Serial data bus 1
5
EN1
Active High Bus 1 enable Input
6
SCL2
Serial clock bus 2
7
SDA2
Serial data bus 2
8
GND
Supply ground
9
EN2
Active High Bus 2 enable Input
10
SCL3
Serial clock bus 3
11
SDA3
Serial data bus 3
12
EN3
Active High Bus 3 enable Input
13
SCL4
Serial clock bus 4
14
SDA4
Serial data bus 4
15
EN4
Active High Bus 4 enable Input
16
V
CC
Supply power
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
16-pin plastic SO (narrow)
­40 to +85
°
C
PCA9516D
SOT109-1
16-pin plastic TSSOP
­40 to +85
°
C
PCA9516PW
SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
1.
The maximum system operating frequency may be less than 400 KHz because of the delays added by the repeater.
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
3
Hub
Logic
V
CC
SCL4
SCL0
SU01396
Buffer
SCL1
Buffer
SCL2
Buffer
EN1
Buffer
SCL3
Buffer
Hub
Logic
SDA4
SDA0
Buffer
SDA1
Buffer
SDA2
Buffer
Buffer
SDA3
Buffer
PCA9516
EN2
EN4
EN3
GND
Figure 2. Block Diagram: PCA9516
A more detailed view of Figure 2 buffer is shown in Figure 3.
SW00712
Data
Enable
To output
In
z
Inc
Figure 3.
The output pull-down of each internal buffer is set for approximately
0.5 V, while the input threshold of each internal buffer is set about
0.07 V lower, when the output is internally driven low. This prevents
a lock-up condition from occurring.
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
4
FUNCTIONAL DESCRIPTION
The PCA9516 BiCMOS integrated circuit is a five way hub repeater,
which enables I
2
C and similar bus systems to be expanded with
only one repeater delay and no functional degradation of system
performance.
The PCA9516 BiCMOS integrated circuit contains five bi-directional,
open drain buffers specifically designed to support the standard
low-level-contention arbitration of the I
2
C-bus. Except during
arbitration or clock stretching, the PCA9516 acts like five pairs of
non-inverting, open drain buffers, one for SDA and one for SCL.
Enable
The enable pins EN1 through EN4 are active high and have internal
pull-up resistors. Each enable pin ENn controls its associated SDAn
and SCLn ports. When low the ENn pin blocks the inputs from SDAn
and SCLn as well as disabling the output drivers on the SDAn and
SCLn pins. The enable pins should only change state when both the
global bus and the local port are in an idle state to prevent system
failures.
The active high enable pins allow the use of open drain drivers
which can be wire-ORed to create a distributed enable where either
centralized control signal (master) or spoke signal (submaster) can
enable the channel when it is idle.
I
2
C Systems
As with the standard I
2
C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I
2
C-bus). The size of these
pull-up resistors depends on the system, but each side of the
repeater must have a pull-up resistor. This part designed to work
with standard mode and fast mode I
2
C devices in addition to SMBus
devices. Standard mode I
2
C devices only specify 3 mA output drive,
this limits the termination current to 3 mA in a generic I
2
C system
where standard mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used.
Please see Application Note AN255
"I
2
C & SMBus Repeaters, Hubs
and Expanders" for additional information on sizing resistors and
precautions when using more than one PCA9515/PCA9516 in a
system or using the PCA9515/16 in conjunction with the P82B96.
APPLICATION INFORMATION
A typical application is shown in Figure 4. In this example, the
system master is running on a 3.3 V I
2
C-bus while the slave is
connected to a 5 V bus. All buses run at 100 kHz unless slave 3 and
4 are isolated and then the master bus and slave 1 and 2 can run at
400 kHz.
Any segment of the hub can talk to any other segment of the hub.
Bus masters and slaves can be located on all five segments with
400 pF load allowed on each segment.
The PCA9516 is 5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
When one side of the PCA9516 is pulled low by a device on the
I
2
C-bus, a CMOS hysteresis type input detects the falling edge and
causes an internal driver on the other side to turn on, thus causing
the other side to also go low. The side driven low by the PCA9516
will typically be at V
OL
= 0.5 V.
In order to illustrate what would be seen in a typical application,
refer to Figures 5 and 6. If the bus master in Figure 4 were to write
to the slave through the PCA9516, we would see the waveform
shown in Figure 5 on Bus 0. This looks like a normal I
2
C
transmission until the falling edge of the 8th clock pulse. At that
point, the master releases the data line (SDA) while the slave pulls it
low through the PCA9516. Because the V
OL
of the PCA9516 is
typically around 0.5 V, a step in the SDA will be seen. After the
master has transmitted the 9th clock pulse, the slave releases the
data line.
SW00923
BUS
MASTER
SLAVE 1
PCA9516
SDA
SDA0
SDA
SCL
SCL0
SCL
EN1
3.3 V
5 V
SDA1
SCL1
EN2
EN3
EN4
SLAVE 2
SDA
SCL
3.3 V
SDA2
SCL2
SLAVE 3
SDA
SCL
5 V
SDA3
SCL3
SLAVE 4
SDA
SCL
5 V
SDA4
SCL4
400 kHz
400 kHz
400 kHz
100 kHz
100 kHz
Figure 4. Typical application
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
5
9th CLOCK PULSE
V
OL
OF MASTER
V
OL
OF PCA9516
2 V/DIV
SW00965
Figure 5. Bus 0 waveform
On the Bus 1 side of the PCA9516, the clock and data lines would
have a positive offset from ground equal to the V
OL
of the PCA9516.
After the 8th clock pulse, the data line will be pulled to the V
OL
of the
slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events
on Bus 1 require that the V
OL
of the devices on Bus 1 be 70 mV
below the V
OL
of the PCA9516 (see V
OL
­ V
ilc
in the DC
Characteristics section) to be recognized by the PCA9516 and then
transmitted to Bus 0.
9th CLOCK PULSE
V
OL
OF SLAVE
V
OL
OF PCA9516
2 V/DIV
SW00966
Figure 6. Bus 1 waveform
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
6
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND.
LIMITS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
CC
to GND
Supply voltage range V
CC
­0.5
+7
V
V
bus
Voltage range I
2
C-bus, SCL or SDA
­0.5
+7
V
I
DC current (any pin)
--
50
mA
P
tot
Power dissipation
--
300
mW
T
stg
Storage temperature range
­55
+125
°
C
T
amb
Operating ambient temperature range
­40
+85
°
C
DC ELECTRICAL CHARACTERISTICS
V
DD
= 3.0 to 3.6 V; GND = 0 V; T
amb
= ­40 to +85
°
C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CC
DC supply voltage
3.0
3.3
3.6
V
I
CCH
Quiescent supply current,
both channels HIGH
V
CC
= 3.6 V;
SDAn = SCLn = V
CC
--
7
10
mA
I
CCL
Quiescent supply current,
both channels LOW
V
CC
= 3.6 V;
one SDA and one SCL = GND,
other SDA and SCL open
--
6.8
10
mA
I
CCLc
Quiescent supply current in contention
V
CC
= 3.6 V;
SDAn = SCLn = GND
--
7
10
mA
Input SCL; input/output SDA
V
IH
High-level input voltage
0.7 V
CC
--
5.5
V
V
IL
Low-level input voltage (Note 1)
­0.5
--
0.3 V
CC
V
V
ILc
Low-level input voltage contention
(Note 1)
­0.5
--
0.4
V
V
IK
Input clamp voltage
I
I
= ­18 mA
--
--
­1.2
V
I
I
Input leakage current
V
I
= 3.6 V
--
--
±
1
µ
A
I
IL
Input current LOW, SDA, SCL
V
I
= 0.2 V, SDA, SCL
--
--
5
µ
A
V
OL
Low level output
I
OL
= 0 or 6 mA
0.47
.52
0.6
V
V
OL
­V
ILc
Low level input voltage below
output low level voltage
Guaranteed by design
--
--
70
mV
I
OH
Output high level leakage current
V
O
= 3.6 V
--
--
10
µ
A
C
I
Input capacitance
V
I
= 3 V or 0 V
--
6
10
pF
Enable 1­4
V
IL
LOW level input voltage
­0.5
--
0.8
V
V
IH
HIGH level input voltage
2.0
--
5.5
V
I
IL
Input current LOW, EN1­EN4
V
I
= 0.2 V, EN1­EN4
--
10
30
µ
A
I
LI
Input leakage current
­1
--
1
µ
A
C
I
Input capacitance
V
I
= 3.0 V or 0 V
--
6
7
pF
NOTE:
1. V
IL
specification is for enable input and the first low level seen by the SDAx/SCLx lines. V
ILc
is for the second and subsequent low levels
seen by the SDAx/SCLx lines.
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
7
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
PHL
Propagation delay
Waveform 1
57
115
170
ns
t
PLH
Propagation delay
Waveform 1
33
55
78
ns
t
THL
Transition time
Waveform 1
67
ns
t
TLH
Transition time
Waveform 1; Note 1
135
ns
t
SET
Enable to Start condition
100
ns
t
HOLD
Enable after Stop condition
100
ns
NOTE:
1. The t
TLH
transition time is guaranteed with loads of 1.35 k
pull-up resistance and 7 pF load capacitance, plus an additional 50 pF load
capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and
transition times.
AC WAVEFORMS
3.3 V
0.1 V
1.5 V
1.5 V
INPUT
OUTPUT
3.3 V
V
OL
t
PHL
t
PLH
80%
20%
1.5 V
1.5 V
80%
20%
t
THL
t
TLH
SW00646
Waveform 1.
TEST CIRCUIT
DEFINITIONS
R
L
=
Load resistor; 1.35 k
C
L
=
Load capacitance includes jig and probe capacitance;
7 pF
R
T
=
Termination resistance should be equal to Z
OUT
of
pulse generators.
PULSE
GENERATOR
V
IN
D.U.T.
V
OUT
C
L
V
CC
R
L
Test Circuit for Open Drain Outputs
R
T
SW00792
V
CC
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
8
SO16:
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
9
TSSOP16:
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
Philips Semiconductors
Product data
PCA9516
5-channel I
2
C hub
2002 May 13
10
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent
to use the components in the I
2
C system provided the system conforms to the
I
2
C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
©
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Date of release: 05-02
Document order number:
9397 750 09815
Philips
Semiconductors
Data sheet status
[1]
Objective data
Preliminary data
Product data
Product
status
[2]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.