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Part Number BST86

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DATA SHEET
Product specification
File under Discrete Semiconductors, SC13b
April 1995
DISCRETE SEMICONDUCTORS
BST86
N-channel enhancement mode
vertical D-MOS transistor
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST86
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in SOT89
envelope and designed for use as
Surface Mounted Device (SMD) in
thin and thick-film circuits for
application with relay, high-speed and
line-transformer drivers.
FEATURES
·
Direct interface to C-MOS, TTL,
etc.
·
High-speed switching
·
No second breakdown
QUICK REFERENCE DATA
PINNING - SOT89
Drain-source voltage
V
DS
max.
180 V
Drain-source voltage (non-repetitive peak;
t
p
2 ms)
V
DS(SM)
max.
200 V
Gate-source voltage (open drain)
±
V
GSO
max.
20 V
Drain current (DC)
I
D
max.
300 mA
Total power dissipation up to T
amb
= 25
°
C
P
tot
max.
1 W
Drain-source ON-resistance
typ.
max.
7
10
I
D
= 15 mA; V
GS
= 3 V
R
DS(on)
Transfer admittance
I
D
= 300 mA; V
DS
= 15 V
Y
fs
typ.
250 mS
1
= source
2
= drain
3
= gate
PIN CONFIGURATION
Fig.1 Simplified outline and symbol.
Marking: K0
handbook, halfpage
1
2
3
MAM355
s
d
g
Bottom view
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST86
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
THERMAL RESISTANCE
Note
1. Transistor mounted on a ceramic substrate of 2.5 cm
2
and thickness of 0.7 mm.
Drain-source voltage
V
DS
max.
180 V
Drain-source voltage (non-repetitive peak; t
p
2 ms)
V
DS(SM)
max.
200 V
Gate-source voltage (open drain)
±
V
GSO
max.
20 V
Drain current (DC)
I
D
max.
300 mA
Drain current (peak)
I
DM
max.
800 mA
Total power dissipation up to T
amb
= 25
°
C (note 1)
P
tot
max.
1 W
Storage temperature range
T
stg
-
65 to + 150
°
C
Junction temperature
T
j
max.
150
°
C
From junction to ambient (note 1)
R
th j-a
=
125 K/W
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST86
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified
Drain-source breakdown voltage
I
D
= 100
µ
A; V
GS
= 0
V
(BR)DSS
min.
180 V
Drain-source leakage current
V
DS
= 120 V; V
GS
= 0
I
DSS
max.
10
µ
A
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
I
GSS
max.
100 nA
Gate threshold voltage
min.
max.
0.7
2.7
V
V
I
D
= 100
µ
A; V
DS
= V
GS
V
GS(th)
Drain-source ON-resistance
typ.
max.
7
10
I
D
= 15 mA; V
GS
= 3 V
R
DS(on)
I
D
= 300 mA; V
GS
= 10 V
R
DS(on)
typ.
6
Transfer admittance
I
D
= 300 mA; V
DS
= 15 V
Y
fs
typ.
250 mS
Input capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
C
iss
typ.
max.
50
65
pF
pF
Output capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
C
oss
typ.
max.
20
30
pF
pF
Feedback capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
C
rss
typ.
max.
6
10
pF
pF
Switching times (see as 2 and 3)
I
D
= 300 mA; V
DD
= 50 V; V
GS
= 0 to 10 V
t
on
t
off
max.
max.
10
15
ns
ns
April 1995
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST86
Fig.2 Switching times test circuit.
handbook, halfpage
MBB691
50
VDD = 50 V
ID
10 V
0 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB692
10 %
90 %
90 %
10 %
ton
toff
OUTPUT
INPUT
Fig.4 T
j
= 25
°
C; typical values.
handbook, halfpage
14
4
ID
(mA)
RDSon (
)
6
8
10
12
10
3
10
2
10
MDA169
(1)
(2)
(3)
(1) V
GS
= 10 V.
(2) V
GS
= 5 V.
(3) V
GS
= 4 V.
Fig.5 T
j
= 25
°
C; V
DS
= 10 V; typ. values.
handbook, halfpage
0
10
1
0
VGS (V)
ID
(A)
0
.
2
0
.
4
0
.
6
0
.
8
2
4
6
8
MDA170