Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- PINNING - SOT223
- QUICK REFERENCE DATA
- LIMITING VALUES
- THERMAL CHARACTERISTICS
- CHARACTERISTICS
- PACKAGE OUTLINE
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
DATA SHEET
Product specification
Supersedes data of 1996 Jun 13
File under Discrete Semiconductors, SC07
1996 Aug 05
DISCRETE SEMICONDUCTORS
BSP255
P-channel enhancement mode
vertical D-MOS transistor
1996 Aug 05
2
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP255
FEATURES
·
Direct interface to C-MOS, TTL etc
·
Low threshold voltage
·
High speed switching
·
No secondary breakdown.
APPLICATIONS
·
Line current interrupter in telephone sets
·
Relay, high speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a 4-pin plastic SOT223 SMD package.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT223
PIN
SYMBOL
DESCRIPTION
1
g
gate
2
d
drain
3
s
source
4
d
drain
Fig.1 Simplified outline and symbol.
handbook, halfpage
MAM121
4
1
2
3
Top view
s
d
g
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage (DC)
-
-
300
V
V
SD
source-drain diode forward voltage
I
S
=
-
0.5 A
-
-
1.8
V
V
GS
gate-source voltage (DC)
-
±
20
V
V
GSth
gate-source threshold voltage
I
D
=
-
1 mA; V
DS
= V
GS
-
0.8
-
2
V
I
D
drain current (DC)
T
s
= 100
°
C
-
-
325
mA
R
DSon
drain-source on-state resistance
I
D
=
-
160 mA; V
GS
=
-
10 V
-
17
P
tot
total power dissipation
T
s
= 100
°
C
-
4
W
1996 Aug 05
3
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP255
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. T
s
is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage (DC)
-
-
300
V
V
GS
gate-source voltage (DC)
-
±
20
V
I
D
drain current (DC)
T
s
= 100
°
C; note 1
-
-
325
mA
I
DM
peak drain current
note 2
-
-
1.3
A
P
tot
total power dissipation
T
s
= 100
°
C
-
4
W
T
stg
storage temperature
-
65
+150
°
C
T
j
operating junction temperature
-
65
+150
°
C
Source-drain diode
I
S
source current (DC)
T
s
= 100
°
C
-
-
0.5
A
I
SM
peak pulsed source current
note 2
-
-
2
A
Fig.2 Power derating curve.
handbook, halfpage
0
200
10
0
2
4
6
8
MBH446
50
100
150
Ptot
(W)
Ts (
o
C)
= 0.01; T
S
= 100
°
C.
(1) R
DSon limitation
.
Fig.3 DC SOAR.
handbook, halfpage
MBH445
-
1
-
10
-
1
-
10
-
1
-
10
-
2
-
10
-
3
-
10
2
-
10
3
-
10
VDS (V)
t p
T
P
t
t p
T
=
1 ms
100
µ
s
10 ms
DC
(1)
tp =
10
µ
s
ID
(A)
1996 Aug 05
4
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP255
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-s
thermal resistance from junction to soldering point
12
K/W
Fig.4
Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
handbook, full pagewidth
1
10
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
1
10
2
10
-
1
10
-
6
10
-
5
10
-
4
10
-
3
10
-
2
10
-
1
MBH444
tp (s)
t p
T
P
t
t p
T
=
Rth j-s
(K/W)
=
0.75
1996 Aug 05
5
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP255
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
drain-source breakdown voltage
V
GS
= 0; I
D
=
-
10
µ
A
-
300
-
-
V
V
GSth
gate-source threshold voltage
V
GS
= V
DS
; I
D
=
-
1 mA
-
0.8
-
-
2
V
I
DSS
drain-source leakage current
V
GS
= 0; V
DS
=
-
240 V
-
-
-
100
nA
I
GSS
gate leakage current
V
GS
=
±
20 V; V
DS
= 0
-
-
±
100
nA
R
DSon
drain-source on-state resistance
V
GS
=
-
10 V; I
D
=
-
160 mA
-
-
17
V
GS
=
-
4.5 V; I
D
=
-
80 mA
-
-
20
V
GS
=
-
2.8 V; I
D
=
-
50 mA
-
-
25
C
iss
input capacitance
V
GS
= 0; V
DS
=
-
50 V; f = 1 MHz
-
45
-
pF
C
oss
output capacitance
V
GS
= 0; V
DS
=
-
50 V; f = 1 MHz
-
15
-
pF
C
rss
reverse transfer capacitance
V
GS
= 0; V
DS
=
-
50 V; f = 1 MHz
-
3
-
pF
Q
g
total gate charge
V
GS
=
-
10 V; V
DD
=
-
50 V;
I
D
=
-
160 mA; T
amb
= 25
°
C
-
2.3
-
nC
Q
gs
gate-source charge
V
GS
=
-
10 V; V
DD
=
-
50 V;
I
D
=
-
160 mA; T
amb
= 25
°
C
-
0.1
-
nC
Q
gd
gate-drain charge
V
GS
=
-
10 V; V
DD
=
-
50 V;
I
D
=
-
160 mA; T
amb
= 25
°
C
-
0.7
-
nC
Switching times (see Fig.11)
t
d(on)
turn-on delay time
V
GS
= 0 to
-
10 V; V
DD
=
-
50 V;
I
D
=
-
160 mA; R
gen
= 50
-
2.4
-
ns
t
r
rise time
-
1.6
-
ns
t
on
turn-on switching time
-
4
-
ns
t
d(off)
turn-off delay time
V
GS
=
-
10 to 0 V; V
DD
=
-
50 V;
I
D
=
-
160 mA; R
gen
= 50
-
13
-
ns
t
f
fall time
-
12
-
ns
t
off
turn-off switching time
-
25
-
ns
Source-drain diode
V
SD
source-drain forward voltage
V
GD
= 0; I
S
=
-
0.5 A
-
-
-
1.8
V
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