Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS FOR 74HC
- AC CHARACTERISTICS FOR 74HC
- DC CHARACTERISTICS FOR 74HCT
- AC CHARACTERISTICS FOR 74HCT
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT356
8-input multiplexer/register; 3-state
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
FEATURES
·
Non-transparent data latches
·
Transparent address latch
·
Easily expanding
·
Complementary outputs
·
Output capability: bus driver
·
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT356 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT356 data selectors/multiplexers contain full
on-chip binary decoding, to select one-of-eight data
sources. The data select address is stored in transparent
latches that are enabled by a LOW on the latch enable
input LE.
Data on the 8 input lines (D
0
to D
7
) is clocked into a
edge-triggered data register by a LOW-to-HIGH transition
of the clock (CP).
When the output enable input OE
1
= HIGH, OE
2
= HIGH
or OE
3
= LOW, the outputs go to the high impedance
OFF-state.
Operation of these output enable inputs does not affect the
state of the latches and register.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W):
P
D
= C
PD
×
V
CC
2
×
f
i
+
(C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC
2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
S
n
, LE to Y, Y
24
25
ns
CP to Y, Y
20
22
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
123
125
pF
December 1990
3
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
8, 7, 6, 5, 4, 3, 2, 1
D
0
to D
7
data inputs
9
CP
clock input data (LOW-to-HIGH, edge-triggered)
10
GND
ground (0 V)
11
LE
address latch enable input (active LOW)
14, 13, 12
S
0
, S
1
, S
2
select inputs
15, 16
OE
1
, OE
2
output enable inputs (active LOW)
17
OE
3
output enable input (active HIGH)
18
Y
3-state multiplexer output (active LOW)
19
Y
3-state multiplexer output (active HIGH)
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
FUNCTION TABLE
Notes
1. This column shows the input address set-up with LE = LOW (address latch is transparent).
2. CP is HIGH, LOW or
.
3. D
0n
to D
7n
= data present at inputs D
0
to D
7
when the data latch clock made the transition from LOW-to-HIGH
D
0p
to D
7p
= data previously latched into the data latch by the LOW-to-HIGH transition of the data latch clock
H = HIGH voltage level
L = LOW voltage level
X = don't care
= LOW-to-HIGH CP transition
= HIGH-to-LOW CP transition
Z = high impedance OFF-state
INPUTS
OUTPUTS
DESCRIPTION
ADDRESS
(1)
CP
OUTPUT ENABLE
Y
Y
S
2
S
1
S
0
OE
1
OE
2
OE
3
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
X
X
L
Z
Z
Z
Z
Z
Z
outputs in
high impedance
OFF-state
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
D
0n
D
1n
D
2n
D
3n
D
0n
D
1n
D
2n
D
3n
data is clocked
into latch
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
D
4n
D
5n
D
6n
D
7n
D
4n
D
5n
D
6n
D
7n
L
L
L
L
L
L
H
H
L
H
L
H
(2)
(2)
(2)
(2)
L
L
L
L
L
L
L
L
H
H
H
H
D
0p
D
1p
D
2p
D
3p
D
0p
D
1p
D
2p
D
3p
outputs do not
change states
H
H
H
H
L
L
H
H
L
H
L
H
(2)
(2)
(2)
(2)
L
L
L
L
L
L
L
L
H
H
H
H
D
4p
D
5p
D
6p
D
7p
D
4p
D
5p
D
6p
D
7p
December 1990
5
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
Fig.4 Functional diagram.
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