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1
PS8468 05/03/00
Product Features
·
High-speed, to 140 MHz
·
Low-noise non-inverting 1-18 buffer
·
Supports up to four SDRAM DIMMs
·
Low skew (< 250ps) between any two output clocks
·
I
2
C Serial Configuration interface
·
Multiple V
DD
, V
SS
pins for noise reduction
·
3.3V power supply voltage
·
Separate Hi-Z pin for testing
·
48-pin SSOP package (V)
Logic Block Diagram
Description
The PI6C180B, a high-speed low-noise 1-18 noninverting buffer
designed for 140 MHz SDRAM clock buffer applications.
At power up all SDRAM output are enabled and active. The I
2
C
Serial control may be used to individually activate/deactivate any
of the 18 output drivers.
The output enable (OE) pin may be pulled low to put all outputs in a
Hi-Z state.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips.
SDRAM17
SDRAM2
SDRAM1
SDRAM0
BUF_IN
OE
SDATA
SCLOCK
SDRAM3
I2C
I/O
Product Pin Configuration
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PI6C180B
Precision 1-18 Clock Buffer
NC
1
NC
2
V
DD0
3
SDRAM0
4
SDRAM1
5
V
SS0
6
V
DD1
7
SDRAM2
8
SDRAM3
9
V
SS1
10
BUF_IN
11
V
DD2
12
SDRAM4
13
SDRAM5
14
V
SS2
15
V
DD3
16
SDRAM6
17
SDRAM7
18
V
SS3
19
V
DD4
20
SDRAM16
21
V
SS4
22
V
DDIIC
23
SDATA
24
NC
NC
V
DD9
SDRAM15
SDRAM14
V
SS9
V
DD8
SDRAM13
SDRAM12
48
V
SS8
47
OE
46
V
DD7
45
SDRAM11
44
SDRAM10
43
V
SS7
42
V
DD6
41
SDRAM9
40
SDRAM8
39
V
SS6
38
V
DD5
37
SDRAM17
36
V
SS5
35
V
SS
IIC
34
SCLOCK
33
32
31
30
29
28
27
26
25
48-Pin
V
2
PS8468 05/03/00
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PI6C180B
Precision 1-18 Clock Buffer
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Product Pin Description
OE Functionality
PI6C180 I
2
C Address Assignment
Notes:
1. Used for test purposes only
2. Buffers are non-inverting
PI6C180B Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Note:
Inactive means outputs are
held LOW and are disabled
from switching.
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(
PI6C180B
Precision 1-18 Clock Buffer
3
PS8468 05/03/00
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2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C180B is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLOCK is HIGH indicates a start condition. A LOW to HIGH
transition on SDATAwhile SCLOCK is HIGH is a stop condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the devices
own address is detected, PI6C180B generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. Command Code byte, and
2. Byte Count byte.
Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
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(
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................. 65°C to +150°C
Ambient Temperature with Power Applied .............................. 0°C to +70°C
3.3V Supply Voltage to Ground Potential .............................. 0.5V to +4.6V
DC Input Voltage .................................................................... 0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Supply Current (V
DD
= +3.465V, C
LOAD
= Max.)
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PS8468 05/03/00
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PI6C180B
Precision 1-18 Clock Buffer
SDRAM Clock Buffer Operating Specification
AC Timing
DC Operating Specifications
(V
DD
= +3.3V ±5%, T
A
= 0°C 70°C)
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PI6C180B
Precision 1-18 Clock Buffer
5
PS8468 05/03/00
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1.5V
1.5V
t
phl
t
plh
1.5V
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500
resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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