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Part Number NTB52N10

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©
Semiconductor Components Industries, LLC, 2002
March, 2002 ­ Rev. 1
1
Publication Order Number:
NTB52N10/D
NTB52N10
Product Preview
Power MOSFET
52 Amps, 100 Volts
N­Channel Enhancement­Mode D
2
PAK
Features
·
Source­to­Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
·
Avalanche Energy Specified
·
I
DSS
and R
DS(on)
Specified at Elevated Temperature
·
Mounting Information Provided for the D
2
PAK Package
Typical Applications
·
PWM Motor Controls
·
Power Supplies
·
Converters
MAXIMUM RATINGS
(T
J
= 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain­to­Source Voltage
V
DSS
100
Vdc
Drain­to­Source Voltage (R
GS
= 1.0 M
)
V
DGR
100
Vdc
Gate­to­Source Voltage
­ Continuous
­ Non­Repetitive (t
p
v
10 ms)
V
GS
V
GSM
"
20
"
40
Vdc
Drain Current
­ Continuous @ T
A
= 25
°
C
­ Continuous @ T
A
= 100
°
C
­ Pulsed (Note 2.)
I
D
I
D
I
DM
52
40
156
Adc
Total Power Dissipation @ T
A
= 25
°
C
Derate above 25
°
C
Total Power Dissipation @ T
A
= 25
°
C (Note 1.)
P
D
178
1.43
2.0
Watts
W/
°
C
Watts
Operating and Storage Temperature Range
T
J
, T
stg
­55 to
+150
°
C
Single Pulse Drain­to­Source Avalanche
Energy ­ Starting T
J
= 25
°
C
(V
DD
= 50 Vdc, V
GS
= 10 Vdc,
I
L(pk)
= 40 A, L = 1.0 mH, R
G
= 25
)
E
AS
800
mJ
Thermal Resistance
­ Junction­to­Case
­ Junction­to­Ambient
­ Junction­to­Ambient (Note 1.)
R
JC
R
JA
R
JA
0.7
62.5
50
°
C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
T
L
260
°
C
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu. Area 0.412 in
2
).
2. Pulse Test: Pulse Width = 10
µ
s, Duty Cycle = 2%.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
52 AMPERES
100 VOLTS
30 m
@ V
GS
= 10 V
Device
Package
Shipping
ORDERING INFORMATION
N­Channel
D
S
G
MARKING DIAGRAM
& PIN ASSIGNMENT
NTB52N10 = Device Code
LL
= Location Code
Y
= Year
WW
= Work Week
NTB52N10
LLYWW
1
Gate
3
Source
4
Drain
2
Drain
1
2
3
4
D
2
PAK
CASE 418B
STYLE 2
NTB52N10
D
2
PAK
50 Units/Rail
NTB52N10T4
D
2
PAK
800/Tape & Reel
http://onsemi.com
NTB52N10
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2
ELECTRICAL CHARACTERISTICS
(T
C
= 25
°
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain­to­Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
µ
Adc)
Temperature Coefficient (Positive)
V
(BR)DSS
100
­
­
160
­
­
Vdc
mV/
°
C
Zero Gate Voltage Drain Current
(V
GS
= 0 Vdc, V
DS
= 100 Vdc, T
J
= 25
°
C)
(V
GS
= 0 Vdc, V
DS
= 100 Vdc, T
J
= 125
°
C)
I
DSS
­
­
­
­
5.0
50
µ
Adc
Gate­Body Leakage Current (V
GS
=
±
20
Vdc, V
DS
= 0 Vdc)
I
GSS
­
­
±
100
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
V
DS
= V
GS,
I
D
= 250
µ
Adc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
­
2.92
­8.75
4.0
­
Vdc
mV/
°
C
Static Drain­to­Source On­State Resistance
(V
GS
= 10 Vdc, I
D
= 26 Adc)
(V
GS
= 10 Vdc, I
D
= 26 Adc, T
J
= 125
°
C)
R
DS(on)
­
­
0.023
0.050
0.030
0.060
Drain­to­Source On­Voltage
(V
GS
= 10 Vdc, I
D
= 52 Adc)
V
DS(on)
­
1.25
1.45
Vdc
Forward Transconductance (V
DS
= 26 Vdc, I
D
= 10 Adc)
g
FS
­
31
­
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vd
V
0 Vd
C
iss
­
2250
3150
pF
Output Capacitance
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
oss
­
620
860
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
­
135
265
SWITCHING CHARACTERISTICS (Notes 3. & 4.)
Turn­On Delay Time
t
d(on)
­
15
25
ns
Rise Time
(V
DD
= 80 Vdc, I
D
= 52 Adc,
V
GS
= 10 Vdc
t
r
­
95
180
Turn­Off Delay Time
V
GS
= 10 Vdc,
R
G
= 9.1
)
t
d(off)
­
74
150
Fall Time
R
G
9.1
)
t
f
­
100
190
Total Gate Charge
(V
80 Vd
I
52 Ad
Q
tot
­
72
135
nC
Gate­to­Source Charge
(V
DS
= 80 Vdc, I
D
= 52 Adc,
V
GS
= 10 Vdc)
Q
gs
­
13
­
Gate­to­Drain Charge
V
GS
= 10 Vdc)
Q
gd
­
37
­
BODY­DRAIN DIODE RATINGS (Note 3.)
Diode Forward On­Voltage
(I
S
= 52 Adc, V
GS
= 0 Vdc)
(I
S
= 37 Adc, V
GS
= 0 Vdc, T
J
= 125
°
C)
V
SD
­
­
1.06
0.95
1.5
­
Vdc
Reverse Recovery Time
(I
52 Ad
V
0 Vd
t
rr
­
148
­
ns
(I
S
= 52 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/
µ
s)
t
a
­
106
­
dI
S
/dt = 100 A/
µ
s)
t
b
­
42
­
Reverse Recovery Stored Charge
Q
RR
­
0.66
­
µ
C
3. Pulse Test: Pulse Width = 300
µ
s max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.
NTB52N10
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3
Figure 1. On­Region Characteristics
V
DS
, DRAIN­TO­SOURCE VOLTAGE (VOLTS)
100
60
50
40
30
20
10
10
7
6
5
4
3
2
1
0
Figure 2. Transfer Characteristics
V
GS
, GATE­TO­SOURCE VOLTAGE (VOLTS)
8
6
5
4
3
2
100
60
50
40
30
20
10
0
0
Figure 3. On­Resistance versus Drain Current
and Temperature
I
D
, DRAIN CURRENT (AMPS)
0.05
0.04
0.03
0.01
50
40
30
20
10
Figure 4. On­Resistance versus Drain Current
and Gate Voltage
I
D
, DRAIN CURRENT (AMPS)
40
30
20
10
0
0.04
0.03
0.02
0.01
0
0
0.05
Figure 5. On­Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
°
C)
2.5
2.25
2.0
1.75
1.5
1.25
1.0
0.75
0.5
150
120
90
60
30
0
­30
­60
V
DS
, DRAIN­TO­SOURCE VOLTAGE (VOLTS)
50
40
30
1000
100
10
0.25
0
10,000
Figure 6. Drain­to­Source Leakage Current
versus Voltage
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN­T
O­SOURCE RESIST
ANCE (
W
)
100
60
0.02
R
DS(on)
, DRAIN­T
O­SOURCE RESIST
ANCE (
W
)
100
50
R
DS(on),
DRAIN­T
O­SOURCE RESIST
ANCE (NORMALIZED)
I
DSS
, LEAKAGE (nA)
70
60
100
8
9
60
80
90
V
GS
= 10 V
9 V
T
J
= 25
°
C
T
J
= 25
°
C
T
J
= ­55
°
C
T
J
= 100
°
C
V
DS
10 V
T
J
= 25
°
C
T
J
= ­55
°
C
T
J
= 100
°
C
V
GS
= 10 V
T
J
= 25
°
C
V
GS
= 10 V
V
GS
= 15 V
I
D
= 26 A
V
GS
= 10 V
T
J
= 150
°
C
V
GS
= 0 V
T
J
= 100
°
C
70
80
90
8 V
7 V
6 V
5 V
5.5 V
4 V
4.5 V
7
70
80
90
70
80
90
70
80
90
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain­gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
­ V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn­on and turn­off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
­ V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off­state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on­state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
­10
0
10
15
20
25
GATE­TO­SOURCE OR DRAIN­TO­SOURCE
VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
6000
3000
1000
0
V
GS
V
DS
5000
2000
­5
5
4000
V
GS
= 0 V
V
DS
= 0 V
T
J
= 25
°
C
C
rss
C
iss
C
oss
C
rss
C
iss
NTB52N10
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5
60
0
0.25
DRAIN­TO­SOURCE DIODE CHARACTERISTICS
V
SD
, SOURCE­TO­DRAIN VOLTAGE (VOLTS)
Figure 8. Gate­To­Source and Drain­To­Source
Voltage versus Total Charge
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
R
G
, GATE RESISTANCE (OHMS)
1
10
100
1000
10
t, TIME
(ns)
V
DD
= 80 V
I
D
= 52 A
V
GS
= 10 V
V
GS
= 0 V
T
J
= 25
°
C
Figure 10. Diode Forward Voltage versus Current
V
GS
, GA
TE­T
O­SOURCE VOL
T
AGE (VOL
TS)
100
80
60
40
20
0
10
6
2
0
Q
G
, TOTAL GATE CHARGE (nC)
V
DS,
DRAIN­T
O­SOURCE VOL
T
AGE (VOL
TS)
8
4
20
70
40
0
100
10
50
30
60
0.35
0.45
0.55
0.65
0.75
0.85
0.95
10
20
40
30
50
I
D
= 52 A
T
J
= 25
°
C
V
GS
Q
2
Q
1
Q
T
V
DS
t
r
t
d(off)
t
d(on)
t
f
20
16
12
18
14
1
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain­to­source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25
°
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance ­
General Data and Its Use."
Switching between the off­state and the on­state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
µ
s. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
­ T
C
)/(R
JC
).
A Power MOSFET designated E­FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non­linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E­FETs can withstand the stress of
drain­to­source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
D
can safely be assumed to
equal the values indicated.
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SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t)
, EFFECTIVE
TRANSIENT

THERMAL
RESIST
ANCE
(NORMALIZED)
t, TIME (
µ
s)
0.1
1
0.01
0.1
0.2
0.02
D = 0.5
0.05
0.01
SINGLE PULSE
R
JC
(t) = r(t) R
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
­ T
C
= P
(pk)
R
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
1
10
0.1
0.01
0.001
0.0001
0.00001
T
J
, STARTING JUNCTION TEMPERATURE (
°
C)
E
AS
, SINGLE PULSE DRAIN­T
O­SOURCE
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
1
100
V
DS
, DRAIN­TO­SOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1
A
V
ALANCHE ENERGY
(mJ)
I D
, DRAIN CURRENT
(AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
25
50
75
100
125
200
I
D
= 40 A
10
10
150
Figure 14. Diode Reverse Recovery Waveform
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
100
500
400
300
800
1000
100
V
GS
= 20 V
SINGLE PULSE
T
C
= 25
°
C
600
1 ms
100
µ
s
10 ms
dc
10
µ
s
1000
700
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INFORMATION FOR USING THE D
2
PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
mm
inches
0.33
8.38
0.08
2.032
0.04
1.016
0.63
17.02
0.42
10.66
0.12
3.05
0.24
6.096
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8
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC­59, SC­70/SOT­323, SOD­123, SOT­23, SOT­143,
SOT­223, SO­8, SO­14, SO­16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D
2
PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
"tombstoning" may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
typical stencil for the DPAK and D
2
PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇ
Figure 15. Typical Stencil for DPAK and
D
2
PAK Packages
SOLDER PASTE
OPENINGS
STENCIL
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
·
Always preheat the device.
·
The delta temperature between the preheat and
soldering should be 100
°
C or less.*
·
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10
°
C.
·
The soldering temperature and time shall not exceed
260
°
C for more than 10 seconds.
·
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
°
C or less.
·
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
·
Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
D
2
PAK is not recommended for wave soldering.
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TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating "profile" for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177­189
°
C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
STEP 1
PREHEAT
ZONE 1
"RAMP"
STEP 2
VENT
"SOAK"
STEP 3
HEATING
ZONES 2 & 5
"RAMP"
STEP 4
HEATING
ZONES 3 & 6
"SOAK"
STEP 5
HEATING
ZONES 4 & 7
"SPIKE"
STEP 6
VENT
STEP 7
COOLING
200
°
C
150
°
C
100
°
C
5
°
C
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205
°
TO 219
°
C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
100
°
C
150
°
C
160
°
C
170
°
C
140
°
C
Figure 16. Typical Solder Heating Profile
NTB52N10
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10
PACKAGE DIMENSIONS
D
2
PAK
CASE 418B­03
ISSUE D
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
S
G
D
­T­
M
0.13 (0.005)
T
2
3
1
4
3 PL
K
J
H
V
E
C
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.340
0.380
8.64
9.65
B
0.380
0.405
9.65
10.29
C
0.160
0.190
4.06
4.83
D
0.020
0.035
0.51
0.89
E
0.045
0.055
1.14
1.40
G
0.100 BSC
2.54 BSC
H
0.080
0.110
2.03
2.79
J
0.018
0.025
0.46
0.64
K
0.090
0.110
2.29
2.79
S
0.575
0.625
14.60
15.88
V
0.045
0.055
1.14
1.40
­B­
M
B
NTB52N10
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11
Notes
NTB52N10
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12
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