Semiconductor Components Industries, LLC, 2000

April, 2000 Rev. 1

Publication Order Number:

MC34151/D

MC34151, MC33151

High Speed Dual

MOSFET Drivers

The MC34151/MC33151 are dual inverting high speed drivers

specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.

Typical applications include switching power supplies, dc to dc

converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.

These devices are available in dualinline and surface mount

packages.

Two Independent Channels with 1.5 A Totem Pole Output

Output Rise and Fall Times of 15 ns with 1000 pF Load

CMOS/LSTTL Compatible Inputs with Hysteresis

Undervoltage Lockout with Hysteresis

Low Standby Current

Efficient High Frequency Operation

Enhanced System Performance with Common Switching Regulator

Control ICs

Pin Out Equivalent to DS0026 and MMH0026

Representative Block Diagram

VCC

5.7V

Logic Input A

Logic Input B

Gnd

100k

Drive Output A

Drive Output B

100k

Device

Package

Shipping

ORDERING INFORMATION

MC34151D

SO8

98 Units/Rail

MC34151P

PDIP8

MC33151D

SO8

PDIP8

P SUFFIX

CASE 626

http://onsemi.com

50 Units/Rail

98 Units/Rail

SO8

D SUFFIX

CASE 751

MC33151DR2

SO8

2500 Tape & Reel

MC34151DR2

SO8

2500 Tape & Reel

MC33151P

PDIP8

50 Units/Rail

MARKING

DIAGRAMS

= 3 or 4

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

PIN CONNECTIONS

N.C.

Logic Input A

Gnd

Logic Input B

N.C.

Drive Output A

VCC

Drive Output B

(Top View)

MC33151VDR2

SO8

2500 Units/Rail

ALYW

3x151

AWL

MC3x151P

YYWW

MC34151, MC33151

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MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC

Logic Inputs (Note 1.)

Vin

0.3 to VCC

Drive Outputs (Note 2.)

Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to VCC)

IO(clamp)

1.5
1.0

Power Dissipation and Thermal Characteristics

D Suffix SO8 Package Case 751

Maximum Power Dissipation @ TA = 50

Thermal Resistance, JunctiontoAir

P Suffix 8Pin Package Case 626

Maximum Power Dissipation @ TA = 50

Thermal Resistance, JunctiontoAir

0.56

180

1.0

100

C/W

Operating Junction Temperature

+150

Operating Ambient Temperature

MC34151
MC33151

0 to +70

40 to +85

Storage Temperature Range

Tstg

65 to +150

ELECTRICAL CHARACTERISTICS

(VCC = 12 V, for typical values TA = 25

C, for min/max values TA is the only operating

ambient temperature range that applies [Note 3.], unless otherwise noted.)

Characteristics

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

Input Threshold Voltage High State Logic 1

Input Threshold Voltage

Low State Logic 0

VIH

VIL

2.6

1.75
1.58

0.8

Input Current High State (VIH = 2.6 V)

Input Current

Low State (VIL = 0.8 V)

IIH

IIL

200

500
100

DRIVE OUTPUT

Output Voltage Low State (ISink = 10 mA)

Output Voltage Low State

(ISink = 50 mA)

Output Voltage Low State

(ISink = 400 mA)

Output Voltage

High State (ISource = 10 mA)

Output Voltage High State

(ISource = 50 mA)

Output Voltage High State

(ISource = 400 mA)

VOL

VOH

10.5
10.4

9.5

0.8
1.1
1.7

11.2
11.1

10.9

1.2
1.5
2.5

Output PullDown Resistor

RPD

100

SWITCHING CHARACTERISTICS (TA = 25

Propagation Delay (10% Input to 10% Output, CL = 1.0 nF)

Logic Input to Drive Output Rise
Logic Input to Drive Output Fall

tPLH(in/out)
tPHL(in/out)

35
36

100
100

Drive Output Rise Time (10% to 90%) CL = 1.0 nF

Drive Output Rise Time (10% to 90%)

CL = 2.5 nF

14
31

Drive Output Fall Time (90% to 10%) CL = 1.0 nF

Drive Output Fall Time (90% to 10%)

CL = 2.5 nF

16
32

TOTAL DEVICE

Power Supply Current

Standby (Logic Inputs Grounded)
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)

ICC

6.0

10.5

10
15

Operating Voltage

VCC

6.5

1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. Tlow = 0

C for MC34151

Thigh = +70

C for MC34151

C for MC33151

+85

C for MC33151

MC34151, MC33151

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Figure 1. Switching Characteristics Test Circuit

Figure 2. Switching Waveform Definitions

Figure 3. Logic Input Current versus

Input Voltage

Figure 4. Logic Input Threshold Voltage

versus Temperature

Figure 5. Drive Output LowtoHigh Propagation

Delay versus Logic Overdrive Voltage

Figure 6. Drive Output HightoLow Propagation

Delay versus Logic Input Overdrive Voltage

Vin, INPUT VOLTAGE (V)

, INPUT

CURRENT

(mA)

inI

VCC = 12 V

TA = 25

TA, AMBIENT TEMPERATURE (

, INPUT

THRESHOLD

VOL

T
AGE (V)

VCC = 12 V

Upper Threshold

Low State Output

Lower Threshold

High State Output

Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)

t PLH(IN/OUT)

, DRIVE OUTPUT

PROP

AGA

TION DELA

(ns)

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

Vth(lower)

VCC = 12 V

CL = 1.0 nF

TA = 25

Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)

t PHL(IN/OUT)

, DRIVE OUTPUT

PROP

AGA

TION DELA

(ns)

VCC = 12 V

CL = 1.0 nF

TA = 25

Vth(upper)

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

5.7V

Logic Input

100k

Drive Output

100k

4.7

0.1

5.0 V

0 V

10%

90%

tPHL

tPLH

90%

10%

Logic Input

tr, tf

10 ns

Drive Output

2.4

2.0

1.6

1.2

0.8

0.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

200

160

120

200

160

120

2.0

4.0

6.0

8.0

100

125

1.6

1.2

0.8

0.4

1.0

2.0

3.0

4.0

MC34151, MC33151

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VCC = 12 V

Vin = 5 V to 0 V

CL = 1.0 nF

TA = 25

Figure 7. Propagation Delay

Figure 8. Drive Output Clamp Voltage

versus Clamp Current

Figure 9. Drive Output Saturation Voltage

versus Load Current

Figure 10. Drive Output Saturation Voltage

versus Temperature

Figure 11. Drive Output Rise Time

Figure 12. Drive Output Fall Time

90%

10%

50 ns/DIV

90%

10%

10 ns/DIV

90%

10%

10 ns/DIV

IO, OUTPUT LOAD CURRENT (A)

clamp

,
OUTPUT

CLAMP

VOL

T
AGE (V)

High State Clamp

(Drive Output Driven Above VCC)

VCC

Gnd

Low State Clamp

(Drive Output Driven Below Ground)

VCC = 12 V

s Pulsed Load

120 Hz Rate
TA = 25

IO, OUTPUT LOAD CURRENT (A)

sat

,
OU

URA

(V)

Source Saturation

(Load to Ground)

VCC = 12 V

s Pulsed Load

120 Hz Rate
TA = 25

VCC

Sink Saturation

(Load to VCC)

Gnd

TA, AMBIENT TEMPERATURE (

sat

, OUTPUT

TURA

TION VOL

T
AGE(V)

Source Saturation
(Load to Ground)

Sink Saturation
(Load to VCC)

VCC = 12 V

Isource = 400 mA

Isink = 400 mA

VCC

Isource = 10 mA

Isink = 10 mA

Gnd

Drive Output

Logic Input

VCC = 12 V

Vin = 5 V to 0 V

CL = 1.0 nF

TA = 25

VCC = 12 V

Vin = 5 V to 0 V

CL = 1.0 nF

TA = 25

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.2

0.4

0.6

0.8

1.0

1.2

1.4

100

125

3.0

2.0

1.0

2.0

3.0

2.0

1.0

0.5
0.7

0.9

1.1

1.9
1.7

1.5
1.0
0.8

0.6

MC34151, MC33151

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Figure 13. Drive Output Rise and Fall Time

versus Load Capacitance

Figure 14. Supply Current versus Drive Output

Load Capacitance

Figure 15. Supply Current versus Input Frequency

Figure 16. Supply Current versus Supply Voltage

CL, OUTPUT LOAD CAPACITANCE (nF)

, OUTPUT

RISE-F

ALL

TIME(ns)

t r

VCC = 12 V

VIN = 0 V to 5.0 V

TA = 25

CL, OUTPUT LOAD CAPACITANCE (nF)

I CC

, SUPPL

CURRENT

(mA)

VCC = 12 V

Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25

f = 500 kHz

f = 200 kHz

f = 50 kHz

I CC

, SUPPL

CURRENT

(mA)

Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25

1 VCC = 18 V, CL = 2.5 nF

2 VCC = 12 V, CL = 2.5 nF

3 VCC = 18 V, CL = 1.0 nF

4 VCC = 12 V, CL = 1.0 nF

f, INPUT FREQUENCY (Hz)

I CC

, SUPPL

CURRENT

(mA)

VCC, SUPPLY VOLTAGE (V)

TA = 25

Logic Inputs at VCC

Low State Drive Outputs

Logic Inputs Grounded

High State Drive Outputs

8.0

6.0

4.0

2.0

0.1

1.0

0.1

1.0

100

1.0 M

4.0

8.0

10 k

APPLICATIONS INFORMATION

Description

The MC34151 is a dual inverting high speed driver

specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.

Input Stage

The Logic Inputs have 170 mV of hysteresis with the input

threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to VCC. This allows
the output of one channel to directly drive the input of a
second channel for masterslave operation. Each input has
a 30 k

pulldown resistor so that an unconnected open

input will cause the associated Drive Output to be in a known
high state.

Output Stage

Each totem pole Drive Output is capable of sourcing and

sinking up to 1.5 A with a typical `on' resistance of 2.4

1.0 A. The low `on' resistance allows high output currents
to be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 k

pulldown resistor to keep

the MOSFET gate low when VCC is less than 1.4 V. No over
current or thermal protection has been designed into the
device, so output shorting to VCC or ground must be
avoided.

Parasitic inductance in series with the load will cause the

driver outputs to ring above VCC during the turnon
transition, and below ground during the turnoff transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to VCC for clamping positive voltage
transients. When operating with VCC at 18 V, proper power
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across

MC34151, MC33151

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the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 19, 20, and 21 show a method of using external
Schottky diode clamps to reduce driver power dissipation.

Undervoltage Lockout

An undervoltage lockout with hysteresis prevents erratic

system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold is
5.3 V, yielding about 500 mV of hysteresis.

Power Dissipation

Circuit performance and long term reliability are

enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:

TJ = TA + PD (R

JA)

where:

TJ = Junction Temperature

TA = Ambient Temperature
PD = Power Dissipation

JA = Thermal Resistance Junction to Ambient

There are three basic components that make up total

power to be dissipated when driving a capacitive load with
respect to ground. They are:

PD = PQ + PC + PT

where:

PQ = Quiescent Power Dissipation

PC = Capacitive Load Power Dissipation

PT = Transition Power Dissipation

The quiescent power supply current depends on the

supply voltage and duty cycle as shown in Figure 16. The
device's quiescent power dissipation is:

PQ = VCC ICCL (1D) + ICCH (D)

where:

ICCL = Supply Current with Low State Drive

Outputs

ICCH = Supply Current with High State Drive

Outputs

D = Output Duty Cycle

The capacitive load power dissipation is directly related

to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:

PC = VCC (VOH VOL) CL f

where:

VOH = High State Drive Output Voltage

VOL = Low State Drive Output Voltage

CL = Load Capacitance

f = frequency

When driving a MOSFET, the calculation of capacitive

load power PC is somewhat complicated by the changing
gate to source capacitance CGS as the device switches. To aid
in this calculation, power MOSFET manufacturers provide

gate charge information on their data sheets. Figure 17
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
`on', the gate must be brought to 10 V with respect to the
source. The graph shows that a gate charge Qg of 110 nC is
required when operating the MOSFET with a drain to source
voltage VDS of 400 V.

, GA

TET

OSOURCE

VOL

T
AGE

(V)

Qg, GATE CHARGE (nC)

CGS =

8.0

4.0

120

160

VDS = 100 V

VDS = 400 V

8.9 nF

2.0 nF

MTM15N50
ID = 15 A

TA = 25

Figure 17. GateToSource Voltage

versus Gate Charge

VGS

The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:

PC(MOSFET) = VC Qg f

The flat region from 10 nC to 55 nC is caused by the
draintogate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
the MC34151 at a higher VCC, additional charge can be
provided to bring the gate above 10 V. This will reduce the
`on' resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.

The transition power dissipation is due to extremely short

simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:

PT 9 VCC (1.08 VCC CL f 8 y 104)
PT must be greater than zero.

Switching time characterization of the MC34151 is

performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited
by transistor turnon/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.

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LAYOUT CONSIDERATIONS

High frequency printed circuit layout techniques are

imperative to prevent excessive output ringing and overshoot.
Do not attempt to construct the driver circuit on
wirewrap or plugin prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For

optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
capacitors connected with short leads as close to the VCC pin
and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1

F ceramic in parallel with a 4.7

tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.

Proper printed circuit board layout is extremely

critical and cannot be over emphasized.

The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.

Figure 18. Enhanced System Performance with

Common Switching Regulators

Figure 19. MOSFET Parasitic Oscillations

Figure 20. Direct Transformer Drive

Figure 21. Isolated MOSFET Drive

Series gate resistor Rg may be needed to damp high frequency parasitic

oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gatesource circuit. Rg will decrease the

MOSFET switching speed. Schottky diode D1 can reduce the driver's

power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.

Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver's power dissipation by
preventing the output pins from being driven above VCC and below ground.

VCC

0.1

5.7V

TL494

TL594

100k

Vin

100k

1N5819

Vin

100k

4 X

1N5819

100k

5819

Isolation

Boundary

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Output Load Regulation

IO (mA)

+VO (V)

VO (V)

27.7

13.3

1.0

27.4

12.9

26.4

11.9

25.5

11.2

24.6

10.5

22.6

9.4

Figure 22. Controlled MOSFET Drive

Figure 23. Bipolar Transistor Drive

Figure 24. Dual Charge Pump Converter

The totempole outputs can furnish negative base current for enhanced
transistor turnoff, with the addition of capacitor C1.

The capacitor's equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.

In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET's turnon and
turnoff times.

100k

Vin

Rg(on)

Rg(off)

Base Charge

Removal

100k

Vin

VCC = 15 V

4.7

0.1

5.7V

6.8

1N5819

+ VO

2.0 VCC

100k

6.8 10

1N5819

VCC

330pF

10k

MC34151, MC33151

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PACKAGE DIMENSIONS

PDIP8

P SUFFIX

CASE 62605

ISSUE K

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

NOTE 2

A

B

T

SEATING
PLANE

0.13 (0.005)

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

9.40

10.16

0.370

0.400

6.10

6.60

0.240

0.260

3.94

4.45

0.155

0.175

0.38

0.51

0.015

0.020

1.02

1.78

0.040

0.070

2.54 BSC

0.100 BSC

0.76

1.27

0.030

0.050

0.20

0.30

0.008

0.012

2.92

3.43

0.115

0.135

7.62 BSC

0.300 BSC

0.76

1.01

0.030

0.040

SO8

D SUFFIX

CASE 75106

ISSUE T

SEATING
PLANE

0.25

C B

0.25

X 45

DIM

MIN

MAX

MILLIMETERS

1.35

1.75

0.10

0.25

0.35

0.49

0.19

0.25

4.80

5.00

1.27 BSC

3.80

4.00

5.80

6.20

0.40

1.25

0.25

0.50

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

0.10

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC34151/D

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Part Number MC34151