MC10E452

Semiconductor Components Industries, LLC, 2002

April, 2002 Rev. 5

Publication Order Number:

MC10E452/D

MC10E452, MC100E452

5V ECL 5 Bit Differential

The MC10E/100E452 is a 5-bit differential register with differential

data (inputs and outputs) and clock. The registers are triggered by a
positive transition of the positive clock (CLK) input. A high on the
Master Reset (MR) asynchronously resets all registers so that the Q
outputs go LOW.

The differential input structures are clamped so that the inputs of

unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below VCC.

The fully differential design of the device makes it ideal for very

high frequency applications where a registered data path is necessary.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Differential D, CLK and Q; VBB Reference Available

1100 MHz Min. Toggle Frequency

Asynchronous Master Reset

PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

with VEE = 0 V

NECL Mode Operating Range: VCC = 0 V

with VEE = 4.2 V to 5.7 V

Internal Input Pulldown Resistors, Output Q3 will Default to Low

State When Inputs Are Left Open

ESD Protection: > 1 KV HBM, > 75 V MM

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

Flammability Rating: UL94 code V0 @ 1/8

Oxygen Index 28 to 34

Transistor Count = 315 devices

Device

Package

Shipping

ORDERING INFORMATION

MC10E452FN

PLCC28

37 Units/Rail

MC10E452FNR2

PLCC28

500 Units/Reel

MC100E452FN

PLCC28

37 Units/Rail

MC100E452FNR2

PLCC28

500 Units/Reel

MARKING

DIAGRAMS

= Assembly Location

WL = Wafer Lot
YY = Year
WW = Work Week

PLCC28

FN SUFFIX

CASE 776

MC10E452FN

AWLYYWW

MC100E452FN

AWLYYWW

1 28

http://onsemi.com

Figure 2. Logic Diagram

D0
D0

D1
D1

D2
D2

D3
D3

D4
D4

Q0
Q0

CLK
CLK

VBB

Q1
Q1

Q2
Q2

Q3
Q3

Q4
Q4

MC10E452, MC100E452

http://onsemi.com

PIN DESCRIPTION

PIN

FUNCTION

[

0:4

]

, D

[

0:4

]

ECL Differential Data Inputs

ECL Master Reset Input

CLK, CLK

ECL Differential Clock Input

[

0:4

]

, Q

[

0:4

]

ECL Differential Data Outputs

VBB

Reference Voltage Output

VCC, VCCO

Positive Supply

VEE

Negative Supply

MAXIMUM RATINGS

(Note 1)

Symbol

Parameter

Condition 1

Condition 2

Rating

Units

VCC

PECL Mode Power Supply

VEE = 0 V

VEE

NECL Mode Power Supply

VCC = 0 V

PECL Mode Input Voltage

VEE = 0 V

VCC

PECL Mode In ut Voltage
NECL Mode Input Voltage

VEE 0 V
VCC = 0 V

VCC

VEE

V
V

Iout

Output Current

Continuous
Surge

100

mA
mA

IBB

VBB Sink/Source

0.5

Operating Temperature Range

0 to +85

Tstg

Storage Temperature Range

65 to +150

Thermal Resistance (JunctiontoAmbient)

0 LFPM
500 LFPM

28 PLCC
28 PLCC

63.5
43.5

C/W

Thermal Resistance (JunctiontoCase)

std bd

28 PLCC

22 to 26

C/W

VEE

PECL Operating Range
NECL Operating Range

4.2 to 5.7

5.7 to 4.2

V
V

Tsol

Wave Solder

< 2 to 3 sec @ 248

265

1. Maximum Ratings are those values beyond which device damage may occur.

Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.

VCCO

D4 VCCO Q4 Q4

VCC

CLK

VEE

VBB

Pinout: 28-Lead PLCC

(Top View)

* All VCC and VCCO pins are tied together on the die.

Figure 1. Pinout Assignment

MC10E452, MC100E452

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10E SERIES PECL DC CHARACTERISTICS

VCCx = 5.0 V; VEE = 0.0 V (Note 2)

40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

VOH

Output HIGH Voltage (Note 3)

3980

4070

4160

4020

4105

4190

4090

4185

4280

VOL

Output LOW Voltage (Note 3)

3050

3210

3370

3050

3210

3370

3050

3227

3405

VIH

Input HIGH Voltage (SingleEnded)

3830

3995

4160

3870

4030

4190

3940

4110

4280

VIL

Input LOW Voltage (SingleEnded)

3050

3285

3520

3050

3285

3520

3050

3302

3555

VBB

Output Voltage Reference

3.57

3.7

3.62

3.63

3.65

3.75

3.69

3.81

VIHCMR

Input HIGH Voltage Common Mode
Range (Differential) (Note 4)

2.2

4.6

2.2

4.6

2.2

4.6

IIH

Input HIGH Current

150

IIL

Input LOW Current

0.5

0.3

0.5

0.25

0.3

0.2

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V.

3. Outputs are terminated through a 50

resistor to VCC2 volts.

4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

10E SERIES NECL DC CHARACTERISTICS

VCCx = 0.0 V; VEE = 5.0 V (Note 5)

40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

VOH

Output HIGH Voltage (Note 6)

1020

930

840

980

895

810

910

815

720

VOL

Output LOW Voltage (Note 6)

1950

1790

1630

1950

1790

1630

1950

1773

1595

VIH

Input HIGH Voltage
(SingleEnded)

1170

1005

840

1130

970

810

1060

890

720

VIL

Input LOW Voltage
(SingleEnded)

1950

1715

1480

1950

1715

1480

1950

1698

1445

VBB

Output Voltage Reference

1.43

1.3

1.38

1.37

1.35

1.25

1.31

1.19

VIHCMR

Input HIGH Voltage Common
Mode Range (Differential)
(Note 7)

2.8

0.4

2.8

0.4

2.8

0.4

IIH

Input HIGH Current

150

IIL

Input LOW Current

0.5

0.3

0.5

0.065

0.3

0.2

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V.

6. Outputs are terminated through a 50

resistor to VCC2 volts.

7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

MC10E452, MC100E452

http://onsemi.com

100E SERIES PECL DC CHARACTERISTICS

VCCx = 5.0 V; VEE = 0.0 V (Note 8)

40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

102

VOH

Output HIGH Voltage (Note 9)

3975

4050

4120

3975

4050

4120

3975

4050

4120

VOL

Output LOW Voltage (Note 9)

3190

3295

3380

3190

3255

3380

3190

3260

3380

VIH

Input HIGH Voltage
(SingleEnded)

3835

4050

4120

3835

4120

3835

4120

VIL

Input LOW Voltage
(SingleEnded)

3190

3300

3525

3190

3525

3190

3525

VBB

Output Voltage Reference

3.62

3.74

3.62

3.74

3.62

3.74

3.62

3.74

VIHCMR

Input HIGH Voltage Common
Mode Range (Differential)
(Note 10)

2.2

4.6

2.2

4.6

2.2

4.6

IIH

Input HIGH Current

150

IIL

Input LOW Current

0.5

0.3

0.5

0.25

0.5

0.2

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.

9. Outputs are terminated through a 50

resistor to VCC2 volts.

10. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

100E SERIES NECL DC CHARACTERISTICS

VCCx = 0.0 V; VEE = 5.0 V (Note 11)

40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

102

VOH

Output HIGH Voltage (Note 12)

1025

950

880

1025

950

880

1025

950

880

VOL

Output LOW Voltage (Note 12)

1810

1705

1620

1810

1745

1620

1810

1740

1620

VIH

Input HIGH Voltage
(SingleEnded)

1165

950

880

1165

880

1165

880

VIL

Input LOW Voltage
(SingleEnded)

1810

1700

1475

1810

1475

1810

1475

VBB

Output Voltage Reference

1.38

1.26

1.38

1.26

1.38

1.26

1.38

1.26

VIHCMR

Input HIGH Voltage Common
Mode Range (Differential)
(Note 13)

2.8

0.4

2.8

0.4

2.8

0.4

IIH

Input HIGH Current

150

IIL

Input LOW Current

0.5

0.3

0.5

0.25

0.5

0.2

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.

12. Outputs are terminated through a 50

resistor to VCC2 volts.

13. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.

MC10E452, MC100E452

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AC CHARACTERISTICS

VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 14)

40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

fMAX

Maximum Toggle Frequency

TBD

1.1

TBD

GHz

tPLH
tPHL

Propagation Delay to Output CLK (Diff)

CLK (SE)

425
375
375

600
600
625

850
900
900

475
425
425

600
600
625

800
850
850

Setup Time

175

150

Hold Time

225

200

tRR

Reset Recovery Time

750

450

700

450

tPW

Minimum Pulse Width

CLK

400
400

tskew

Within-Device Skew (Note 15)

tJITTER

CycletoCycle Jitter

TBD

VPP

Minimum Input Swing (Differential)
(Note 16)

150

1000

150

1000

150

1000

tr/tf

Rise/Fall Times 2080%

250

475

725

275

475

675

14. 10 Series: VEE can vary +0.46 V / 0.06 V.

100 Series: VEE can vary +0.46 V / 0.8 V.

15. Within-device skew is defined as identical transitions on similar paths through a device.
16. Minimum input swing for which AC parameters are guaranteed.

V TT = V CC 2.0 V

Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 Termination of ECL Logic Devices.)

Driver
Device

Receiver
Device

V TT

Resource Reference of Application Notes

AN1404

ECLinPS Circuit Performance at NonStandard VIH Levels

AN1405

ECL Clock Distribution Techniques

AN1406

Designing with PECL (ECL at +5.0 V)

AN1503

ECLinPS I/O SPICE Modeling Kit

AN1504

Metastability and the ECLinPS Family

AN1568

Interfacing Between LVDS and ECL

AN1596

ECLinPS Lite Translator ELT Family SPICE I/O Model Kit

AN1650

Using WireOR Ties in ECLinPS Designs

AN1672

The ECL Translator Guide

AND8001

Odd Number Counters Design

AND8002

Marking and Date Codes

AND8020

Termination of ECL Logic Devices

Part Number MC10E452