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Part Number MC100E451

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MC10E451
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©
Semiconductor Components Industries, LLC, 2002
April, 2002 ­ Rev. 4
1
Publication Order Number:
MC10E451/D
MC10E451, MC100E451
5V ECL 6 Bit D Register
Differential Data and Clock
The MC10E/100E451 contains six D-type flip-flops with
single-ended outputs and differential data inputs. The common clock
input is also differential. The registers are triggered by a positive
transition of the positive clock (CLK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to
LOW.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below VCC.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
·
Differential Inputs: Data and Clock
·
VBB Output
·
1100 MHz Min. Toggle Frequency
·
Asynchronous Master Reset
·
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
·
NECL Mode Operating Range: VCC= 0 V
with VEE= ­4.2 V to ­5.7 V
·
Internal Input Pulldown Resistors
·
ESD Protection: > 2 KV HBM, > 200 V MM
·
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
·
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
·
Flammability Rating: UL­94 code V­0 @ 1/8",
Oxygen Index 28 to 34
·
Transistor Count = 348 devices
Device
Package
Shipping
ORDERING INFORMATION
MC10E451FN
PLCC­28
37 Units/Rail
MC10E451FNR2
PLCC­28
500 Units/Reel
MC100E451FN
PLCC­28
37 Units/Rail
MC100E451FNR2
PLCC­28
500 Units/Reel
MARKING
DIAGRAMS
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC­28
FN SUFFIX
CASE 776
MC10E451FN
AWLYYWW
MC100E451FN
AWLYYWW
1 28
1 28
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LOGIC DIAGRAM
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
CLK
CLK
MR
VBB
Q0
Q1
Q2
Q3
Q4
Q5
D
R
D
R
D
R
D
R
D
R
D
R
MC10E451, MC100E451
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2
D1
D1
D2
D2 VCCO
D3
D3
D4
D4
D5
D5
VCCO
Q0
CLK
VBB
CLK
VEE
MR
NC
D0
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
Q5
Q4
VCC
Q3
VCCO
Q2
Q1
D0
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
FUNCTION
D0 ­ D5, D0 ­ D5
ECL Differential Data Input
CLK, CLK
ECL Differential Clock Input
MR
ECL Master Reset Input
Q0 ­ Q5
ECL Data Outputs
VBB
Reference Voltage Output
VCC, VCCO
Positive Supply
VEE
Negative Supply
NC
No Connect
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MC10E451, MC100E451
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3
MAXIMUM RATINGS
(Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
­8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI
VCC
6
V
VI
PECL Mode In ut Voltage
NECL Mode Input Voltage
VEE 0 V
VCC = 0 V
VI
VCC
VI
VEE
6
­6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
±
0.5
mA
TA
Operating Temperature Range
0 to +85
°
C
Tstg
Storage Temperature Range
­65 to +150
°
C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°
C/W
°
C/W
JC
Thermal Resistance (Junction to Case)
std bd
28 PLCC
22 to 26
°
C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
­5.7 to ­4.2
V
V
Tsol
Wave Solder
<2 to 3 sec @ 248
°
C
265
°
C
1. Maximum Ratings are those values beyond which device damage may occur.
10E SERIES PECL DC CHARACTERISTICS
VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
84
101
84
101
84
101
mA
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage (Single Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.63
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
150
150
µ
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.3
0.2
µ
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / ­0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC­2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
10E SERIES NECL DC CHARACTERISTICS
VCCx= 0.0 V; VEE= ­5.0 V (Note 1)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
84
101
84
101
84
101
mA
VOH
Output HIGH Voltage (Note 2)
­1020
­930
­840
­980
­895
­810
­910
­815
­720
mV
VOL
Output LOW Voltage (Note 2)
­1950
­1790
­1630
­1950
­1790
­1630
­1950
­1773
­1595
mV
VIH
Input HIGH Voltage (Single Ended)
­1170
­1005
­840
­1130
­970
­810
­1060
­890
­720
mV
VIL
Input LOW Voltage (Single Ended)
­1950
­1715
­1480
­1950
­1715
­1480
­1950
­1698
­1445
mV
VBB
Output Voltage Reference
­1.38
­1.37
­1.35
­1.25
­1.31
­1.19
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
­2.8
­0.4
­2.8
­0.4
­2.8
­0.4
V
IIH
Input HIGH Current
150
150
150
µ
A
IIL
Input LOW Current
0.5
0.3
0.5
0.065
0.3
0.2
µ
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / ­0.06 V.
2. Outputs are terminated through a 50 ohm resistor to VCC­2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E451, MC100E451
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4
100E SERIES PECL DC CHARACTERISTICS
VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
84
101
84
101
97
116
mA
VOH
Output HIGH Voltage (Note 2)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 2)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single Ended)
3835
4050
4120
3835
4120
4120
3835
4120
4120
mV
VIL
Input LOW Voltage (Single Ended)
3190
3300
3525
3190
3525
3525
3190
3525
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
150
150
µ
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
µ
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / ­0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC­2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
100E SERIES NECL DC CHARACTERISTICS
VCCx= 0.0 V; VEE= ­5.0 V (Note 1)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
84
101
84
101
97
116
mA
VOH
Output HIGH Voltage (Note 2)
­1025
­950
­880
­1025
­950
­880
­1025
­950
­880
mV
VOL
Output LOW Voltage (Note 2)
­1810
­1705
­1620
­1810
­1745
­1620
­1810
­1740
­1620
mV
VIH
Input HIGH Voltage (Single Ended)
­1165
­950
­880
­1165
­880
­880
­1165
­880
­880
mV
VIL
Input LOW Voltage (Single Ended)
­1810
­1700
­1475
­1810
­1475
­1475
­1810
­1475
­1475
mV
VBB
Output Voltage Reference
­1.38
­1.26
­1.38
­1.26
­1.38
­1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
­2.8
­0.4
­2.8
­0.4
­2.8
­0.4
V
IIH
Input HIGH Current
150
150
150
µ
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
µ
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / ­0.8 V.
2. Outputs are terminated through a 50 ohm resistor to VCC­2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
AC CHARACTERISTICS
VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= ­5.0 V (Note 1)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
TBD
1.1
TBD
GHz
tPLH
Propagation Delay to Output
ps
tPHL
CLK (Diff)
475
650
800
475
650
800
475
650
800
CLK (SE)
425
650
850
425
650
850
425
650
850
MR
425
600
850
425
600
850
425
600
850
ts
Setup Time
D
150
­100
150
­100
150
­100
ps
th
Hold Time
D
250
100
250
100
250
100
ps
tRR
Reset Recovery Time
750
600
750
600
750
600
ps
tPW
Minimum Pulse Width
ps
CLK, MR
400
400
400
tSKEW
Within-Device Skew (Note 2.)
100
100
100
ps
tJITTER
Cycle­to­Cycle Jitter
TBD
TBD
TBD
ps
VPP(AC)
Minimum Input Swing (Note 1.)
150
1000
150
1000
150
1000
mV
tr
Rise/Fall Times
ps
tf
(20 - 80%)
275
450
800
275
450
800
275
450
800
1. 10 Series: VEE can vary +0.46 V / ­0.06 V.
100 Series: VEE can vary +0.46 V / ­0.8 V.
1. Minimum input voltage for which AC parameters are guaranteed.
2. Within-device skew is defined as identical transitions on similar paths through a device.
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5
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 ­ Termination of ECL Logic Devices.)
W
Driver
Device
Receiver
Device
Q
D
50
W
50
V TT
Q
D
VTT = VCC ­ 2.0 V
Resource Reference of Application Notes
AN1404
­
ECLinPS Circuit Performance at Non­Standard VIH Levels
AN1405
­
ECL Clock Distribution Techniques
AN1406
­
Designing with PECL (ECL at +5.0 V)
AN1503
­
ECLinPS I/O SPICE Modeling Kit
AN1504
­
Metastability and the ECLinPS Family
AN1568
­
Interfacing Between LVDS and ECL
AN1596
­
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
­
Using Wire­OR Ties in ECLinPS Designs
AN1672
­
The ECL Translator Guide
AND8001
­
Odd Number Counters Design
AND8002
­
Marking and Date Codes
AND8020
­
Termination of ECL Logic Devices