NTE21256
262,144Bit Dynamic Random
Access Memory (DRAM)
Description:
The NTE21256 is a 262,144 word by 1bit dynamic Random Access Memory. This 5Vonly component
is fabricated with Nchannel silicon gate technology.
Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard
16Lead DIP package. Features of this device include single power supply with
±
10% tolerance, on
chip address, date registers which eliminate the need for interface registers, and fully TTL compatible
inputs and outputs, including clocks.
In addition to the usual read, write, and readmodifywrite cycles, the NTE21256 is capable of early
and late write cycles, RASonly refresh, and hidden refresh. Common I/O capability is given by using
early write operation.
The NTE21256 also features page mode which allows highspeed random access of bits in the same
row.
Features:
D
262,144 x 1Bit Organization
D
Single +5V Supply,
±
10% Tolerance
D
Low Power Dissipation:
385mW active (Max)
28mW standby (Max)
D
Access Time: 150ns
D
Cycle Time: 260ns
D
All Inputs and Outputs TTL Compatible
D
OnChip Substrate Bias Generator
D
ThreeState Data Output
D
Read, Write, ReadModifyWrite, RASOnlyRefresh, Hidden Refresh
D
Common I/O Capability using "Early Write" Operation
D
Page Mode Read and Write, ReadWrite
D
256 Refresh Cycles with 4ms Refresh Period
Absolute Maximum Ratings: (Note 1)
Operating Temperature Range, T
opr
0
°
to +70
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
65
°
to +150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage on any pin relative to V
SS
1 to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation, P
D
1W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Out Current (Short Circuit)
50mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Functional Description:
Device Initialization
Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required.
For powerup, an initial pause of 200
µ
s is necessary for the internal bias generator to establish the
proper substrate bias voltage. To initialize the nodes of the dynamic circuitry, a minimum of 8 active
cycles of the Row Address Strobe (RAS) has to be performed. This is also necessary after an ex-
tended inactive state of greater than 4ms.
Addressing (A0A8)
For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row
Address bits are set up on pins A0 through A8 and latched into the row address latches by the Row
Address Strobe (RAS). Then the 9 column address bits are set up on pins A0 through A8 and latched
into the column address latches by the Column Address Strobe (CAS). All input addresses must be
stable on the falling edges of RAS and CAS. It should be noted that RAS is similar to a Chip Enable
in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select acti-
vating the column decoder and the input and output buffers.
Write Enable (WE)
The read or write mode is selected with the WE input. A logic high (V
IH
) on WE dictates read
mode; logic low (V
IL
) dictates write mode. The data input is disabled when read mode is selected.
When WE goes low prior to CAS, data output (DO) will remain in the highimpedance state for the
entire cycle permitting common I/O operation.
Data Input (DI)
Data is written during a write or readmodifywrite cycle. The falling edge of CAS or WE strobes data
into the onchip data latch. In an early write cycle, WE is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times referenced to this signal.
Data Output (DO)
The output is threestate TTL compatible with a fanout of two standard TTL loads. Data Out has
the same polarity as Data In. The output is in a high impedance state until CAS is brought low. In
a read cycle or readwrite cycle, the output is valid after t
RAC
from transition of RAS when t
RCD
(Min)
is satisfied, or after t
CAC
from transition of CAS when the transition occurs after t
RCD
(Max). In an early
write cycle, the output is always in the high impedance state. In a delayed write or readmodifywrite
cycle, the output will follow the sequence for the read cycle. With CAS going high the output returns
to the high impedance state within t
OFF
.
Hidden Refresh
RASonly refresh cycle may take place while maintaining valid output data. This feature is referred
to as Hidden Refresh. Hidden Refresh is performed by holding CAS at V
IL
of a previous memory read
cycle.
Refresh Cycle
A refresh operation must be performed at least every 4ms to retain data. Since the output buffer is
in the high impedance state unless CAS is applied, the RASonly refresh sequence avoids any signal
during refresh. Strobing each of the 256 row addresses (A0 through A7) with RAS, causes all bits
in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve
power.
Page Mode
Pagemode operation allows effectively faster memory access by maintaining the row address and
strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe se-
quential row addresses for the same page is no longer required. The maximum number of columns
that can be addressed in sequence is determined by t
RAS
, the maximum RAS low pulse width.
DC Characteristics: (T
A
= 0
°
to +70
°
C, V
SS
= 0V, V
CC
= +5V
±
10% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input High Voltage (All Inputs)
V
IH
Notes 2, Note3
2.4
V
CC
+1
V
Input Low Voltage (All Inputs)
V
IL
Notes 2, Note3
1.0
0.8
V
Output High Voltage
V
OH
Note 4
2.4
V
Output Low Voltage
V
OL
Note 5
0.4
V
Average V
CC
Supply Current
I
CC1
t
RC
= 260ns, Note 6
70
mA
Standby V
CC
Supply Current
I
CC2
Note 7
5
mA
Average V
CC
Supply Current during
RASonly refresh cycles
I
CC3
Note 6
65
mA
Average V
CC
supply Current during
Page Mode
I
CC4
Note 6
55
mA
Input Leakage Current (Any Input)
I
I (L)
10
µ
A
Output Leakage Current
I
O (L)
CAS at Logic 1, 0
V out
5.5
10
µ
A
Supply Voltage
V
CC
Note 2
4.5
5.5
V
V
SS
0
0
V
Note 2. All voltages referenced to V
SS
.
Note 3. Overshooting and undershooting on input levels of +6.5V or 2V for a period 0f 30ns Max.
will influence function and reliability of the device.
Note 4. I
OH
= 4mA and 100pf load.
Note 5. I
OL
= 4mA and 100pf load.
Note 6. I
CC
depends on frequency of operation. Maximum current is measured at the fastest cycle
rate.
Note 7. RAS and CAS are both at V
IH
.
Capacitance: (Note 6)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Capacitance (A0A8, DI)
C
I1
6
pF
Input Capacitance (RAS, CAS, WE)
C
I2
7
pF
Output Capacitance (DO, CAS = V
IH
to disable output)
C
O
7
pF
Note 6. Effective capacitance calculated from the equation:
C =
I
·
t
V
with
V = 3V or measured with Boonton meter.
AC Test Conditions:
Input Pulse Levels
0 to 3.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise and Fall Times
5ns between 0.8 and 2.4V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Reference Levels
0.8 to 2.4V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Levels
0.4 to 2.4V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
equivelent to 2 standard TTL loads and 100pf
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics: (T
A
= 0
°
to +70
°
C, V
CC
= 5V
±
10%, Note 9, Note 10, Note 11 unless
otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Random Read or Write Cycle Time
t
RC
Note 12
260
ns
ReadModifyWrite Cycle Time
t
RWC
Note 12
310
ns
Access Time from RAS
t
RAC
Notes 13, Note 14
150
ns
Access Time from CAS
t
CAC
Notes 13, Note 15
75
ns
RAS Pulse Width
t
RAS
150
10
4
ns
CAS Pulse Width
t
CAS
75
ns
Refresh Period
t
REF
4
ms
RAS Precharge Time
t
RP
100
ns
CAS to RAS Precharge Time
t
CRP
0
ns
RAS to CAS Delay Time
t
RCD
Note 16
30
75
ns
RAS Hold Time
t
RSH
75
ns
CAS Hold Time
t
CSH
150
ns
Row Address Setup Time
t
ASR
0
ns
Row Address Hold Time
t
RAH
20
ns
Column Address Setup Time
t
ASC
0
ns
Column Address Hold Time
t
CAH
30
ns
Column Address Hold Time referenced to RAS
t
AR
Note 17
105
ns
Transition Time (Rise and Fall)
t
T
Note 9
3
50
ns
Read Command Setup Time
t
RCS
0
ns
Read Command Hold Time referenced to CAS
t
RCH
Note 18
0
ns
Read Command Hold Time referenced to RAS
t
RRH
Note 18
10
ns
Output Buffer TurnOff Delay
t
OFF
Note 19
0
40
ns
Note 9. V
IH
and V
IL
are reference levels to measure timing of input signals. Also, transition times
are measured between V
IH
and V
IL
.
Note10. An initial pause of 200
µ
s is required after powerup followed by a minimum of eight initialization
cycles prior to normal operation.
Note 11. The time parameters specified here are valid for a transition time of t
T
= 5ns for the input signals
Note12. The specification for t
RC
(Min), t
RWC
(Min), and pagemode cycle time (t
PC
) are only used
to indicate cycle time at which proper operation over full temperature range
(0
°
C
T
A
+70
°
C) is assured.
Note13. Measured with a load equivalent to two TTL loads and 100pf.
Note14. Assumes that t
RCD
t
RCD
(Max). If t
RCD
is greater than the maximum recommended value
shown in this table, t
RAC
will increase by the amount that t
RCD
exceeds the value shown.
Note15. Assumes that t
RCD
t
RCD
(Max).
Note16. Operation within the t
RCD
(Max) limit ensures that t
RAC
(Max) can be met. t
RCD
(Max) is spe-
cified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max) limit, then
access time is controlled exclusively by t
CAC
.
Note17. t
RCD
+ t
CAH
t
AR
Min, t
RCD
+ t
DH
t
DHR
Min, t
RCD
+ t
WCH
t
WCR
Min.
Note18. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
Note19. t
OFF
(Max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
AC Characteristics (Cont'd):
(T
A
= 0
°
to +70
°
C, V
CC
= 5V
±
10%, Note 9, Note 10, Note 11
unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Write Command Setup Time
t
WCS
Note 20
0
ns
Write Command Hold Time
t
WCH
45
ns
Write Command Hold Time referenced to RAS
t
WCR
Note 17
120
ns
Write Command Pulse Width
t
WP
45
ns
Write Command to RAS Lead Time
t
RWL
45
ns
Write Command to CAS Lead Time
t
CWL
45
ns
Data in Setup Time
t
DS
Note 21
0
ns
Data in Hold Time
t
DH
Note 21
45
ns
Data in Hold Time referenced to RAS
t
DHR
Note 17
120
ns
CAS to WE Delay
t
CWD
Note 20
75
ns
RAS to WE Delay
t
RWD
Note 20
150
ns
RMW Cycle RAS Pulse Width
t
RRW
200
ns
RMW Cycle CAS Pulse Width
t
CRW
125
ns
Page Mode Cycle Time
t
PC
Note 12
145
ns
Page Mode ReadWrite Cycle Time
t
PRWC
190
ns
Page Mode CAS Precharge Time
t
CP
60
ns
Note 9. V
IH
and V
IL
are reference levels to measure timing of input signals. Also, transition times
are measured between V
IH
and V
IL
.
Note10. An initial pause of 200
µ
s is required after powerup followed by a minimum of eight initialization
cycles prior to normal operation.
Note 11. The time parameters specified here are valid for a transition time of t
T
= 5ns for the input signals
Note12. The specification for t
RC
(Min), t
RWC
(Min), and pagemode cycle time (t
PC
) are only used
to indicate cycle time at which proper operation over full temperature range
(0
°
C
T
A
+70
°
C) is assured.
Note17. t
RCD
+ t
CAH
t
AR
Min, t
RCD
+ t
DH
t
DHR
Min, t
RCD
+ t
WCH
t
WCR
Min.
Note20. t
WCS
, t
CWD
, and t
RWC
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only: If t
WCS
t
WCS
(Min), the cycle is an early write cycle
and the Data Out will remain open circuit (high impedance) throughout the entire cycle; if
t
CWD
t
CWD
(Min) and t
RWD
t
RWD
(Min) the cycle is a readwrite cycle and the Data Out
will contain data read from the selected cell. If neither of the above sets of conditions is satis-
fied, the condition of the Data Out (at access time) is indeterminate.
Note21. t
DS
and t
DH
are referenced to the leading edge of CAS in early write cycles, and to the leading
edge of WE in delayed write of readmodifywrite cycles.